EECS150 Components and Design Techniques for Digital Systems

EECS150 Spring 2004

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Course Grading

  • Homework: 10%
  • Labs: 10%
  • Midterms (2): 20%
  • Final Project: 30%
  • Final Exam: 30%


Required: R. H. Katz, G. Borriello, Contemporary Logic Design, 2nd Ed., Prentice Hall/Pearson Publishing, Upper Saddle River, NJ, 2004. Available in Draft Form and distributed through Copy Central on Hearst west of Euclid. Readings denoted by K&B.
Recommended: M. D. Ciletti, Advanced Digital Design with the Verilog HDL, Prentice Hall/Pearson Publishing, Upper Saddle River, NJ, 2003. Required text from last semester. Lots more Verilog examples than K&B, but not very useful for lecture portion of course.

Catalog Description

EECS150: Components and Design Techniques for Digital Systems. (5)

Three hours of lecture, one hour of discussion, and three hours of laboratory per week. Prerequisites: 61C, Electrical Engineering 40 or 42. Basic building blocks and design methods to contruct synchronous digital systems. Alternative representations for digital systems. Bipolar TTL vs. MOS implementation technologies. Standard logic (SSI, MSI) vs. programmable logic (PLD, FPGA). Finite state machine design. Digital computer building blocks as case studies. Introduction to computer-aided design software. Formal hardware laboratories and substantial design project. Informal software laboratory periodically throughout semester. (F,SP) Katz, Newton, Pister.

  • You must complete your previous week's laboratory and have it checked off completely before the beginning of the current week's lab. You can arrange to do this by making an appointment with your TA, seeing him during his office hours, or having it checked off just before the current week's lab commences at ten minutes after the hour.
  • Do not fall behind--it is virtually impossible to catch up, as the labs become progressively more difficult over the course of the semester.
  • Since the substantial lab project is a major effort involving a lab partner, it is essential that you contact your partner, your TA, and your instructor if you intend to drop the course!
  • Homework assignments are distributed on Thursdays (starting the first week), and collected from the homework box by the door of 125 Cory the following Friday at 2pm (SHARP!). This gives you 8 days to the do the homework and plenty of time to attend discussion section with questions or to consult with the TAs and the instructor.
  • Graded homeworks are returned in the laboratory. Solution sets will be prepared by the readers and will be posted to the web.
  • Homework is graded on effort, not correctness.
  • See calendar on this web page for handouts, assignments, and announcements.
  • Please attend a discussion section to hear about the solutions to the exam. This will usually take place during the week following the return of the exam.
  • Regrades are by written petition only. The petition should succinctly state why you believe that your solution is correct when we believed it to be wrong. These should be given to the instructor. Please note that we do provide partial credit and we grade consistently across all exams. Also note that the midterms (20%) pale in comparison to the final exam (30%) and the final project (30%) in determining your final course grade

Academic Honesty
It is a sad fact of life that cheating sometimes happens. By this we mean claiming work as your own when in fact it is not. Cheating will not be tolerated. While it is OK to discuss the homework assignments, labs, and project with your fellow students, all the work you hand in must be your own. Harsh penalties will be imposed should we detect cheating. Namely a 0 for that portion of the course, and a letter of reprimand to your student file. A second infraction is usually grounds for dismissal from the University.

Switching Lab and Discussion Sections

Discussion: Attend the one you signed up for, at least for a week or two.  Otherwise some discussions will be much too large.  After about the second week of discussion (third of lecture) feel free to attend any discussion you like as long as attendance at that one is reasonable.  We recommend one taught by one of your lab TAs.

Lab: E-mail Greg (gdgib@uclink) with your full name, and which section you're switching from and to, and then attend the lab section you would like to be in.  Evening labs tend to be pretty full, so we may not be able allow all morning to evening switches.  We recommend morning labs! Because there are fewer students your TAs wont be overworked, and therefore they'll be much happier to help.  If you already have a project partner in mind, the two of you must be in the same lab.


The newsgroup for this course is ucb.class.cs150, it is availible from  To get access from off campus you can use a unix newsreader (such as tin) from an instructional server, you may use webnews (see the links page) or you may use AUS (see the links page).

  • The newsgroup will sometimes have duplicate announcements from the webpage.  The webpage is the primary source of course news.
  • Please post a question to the newsgroup rather than e-mail a TA.
  • Feel free to answer questions of other students, but do be sure of your answer.  (Take student written answers with a grain of salt)
  • Academic Honesty rules still apply.  Do not solicit or provide answers on the newsgroup.

Course Goals
  • Understand digital logic at the gate and switch level including both combinational and sequential logic elements.
  • Understand clocking methodologies to manage information flow and preservation of circuit state.
  • Appreciate digital logic specification methods and the compilation process that transforms these into logic networks.
  • Gain experience with computer-aided design tools for implementation with programmable logic devices.
  • Appreciate the advantages/disadvantages between hardware and software implementations of a function.

Course Syllabus
Introduction to modern digital logic design Combinational logic
  • Switch logic and basic gates
  • Boolean algebra
  • Two-level logic
  • Regular logic structures
  • Multi-level networks and transformations
  • Programmable logic devices
  • Time response
  • Case studies
Sequential logic
  • Networks with feedback
  • Basic latches and flip-flops
  • Timing methodologies
  • Registers and counters
  • Programmable logic devices
  • Case studies
Finite state machine design
  • Concepts of FSMs
  • Basic design approach
  • Specification methods
  • State minimization
  • State encoding
  • FSM partitioning
  • Implementation of FSMs
  • Programmable logic devices
  • Case studies
Elements of computers
  • Arithmetic circuits
  • Arithmetic and logic units
  • Register and bus structures
  • Controllers/Sequencers
  • Microprogramming
Computer-aided design tools for logic design
  • Schematic entry
  • State diagram entry
  • Hardware description language entry
  • Compilation to logic networks
  • Simulation
  • Mapping to programmable logic devices
Practical topics
  • Non-gate logic
  • Asynchronous inputs and metastability
  • Memories: RAM and ROM
  • Implementation technologies

ŠUC Berkeley EECS150
Last Updated: 06/08/2004 by [an error occurred while processing this directive]
Greg Gibeling