EECS150 Components and Design Techniques for Digital Systems | |
EECS150 Spring 2004 |
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Sections... |
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Course Grading |
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Textbooks |
Required: R. H. Katz, G. Borriello, Contemporary Logic Design,
2nd Ed., Prentice Hall/Pearson Publishing, Upper Saddle River, NJ,
2004. Available in Draft Form and distributed through Copy Central on Hearst
west of Euclid. Readings denoted by K&B. |
Catalog Description |
EECS150: Components and Design Techniques for Digital Systems. (5) Three hours of lecture, one hour of discussion, and three hours of laboratory per week. Prerequisites: 61C, Electrical Engineering 40 or 42. Basic building blocks and design methods to contruct synchronous digital systems. Alternative representations for digital systems. Bipolar TTL vs. MOS implementation technologies. Standard logic (SSI, MSI) vs. programmable logic (PLD, FPGA). Finite state machine design. Digital computer building blocks as case studies. Introduction to computer-aided design software. Formal hardware laboratories and substantial design project. Informal software laboratory periodically throughout semester. (F,SP) Katz, Newton, Pister. |
Policies |
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Academic Honesty |
It is a sad fact of life that cheating sometimes happens. By this we mean claiming work as your own when in fact it is not. Cheating will not be tolerated. While it is OK to discuss the homework assignments, labs, and project with your fellow students, all the work you hand in must be your own. Harsh penalties will be imposed should we detect cheating. Namely a 0 for that portion of the course, and a letter of reprimand to your student file. A second infraction is usually grounds for dismissal from the University. |
Switching Lab and Discussion Sections |
Discussion: Attend the one you signed up for, at least for a week or two. Otherwise some discussions will be much too large. After about the second week of discussion (third of lecture) feel free to attend any discussion you like as long as attendance at that one is reasonable. We recommend one taught by one of your lab TAs. Lab: E-mail Greg (gdgib@uclink) with your full name, and which section you're switching from and to, and then attend the lab section you would like to be in. Evening labs tend to be pretty full, so we may not be able allow all morning to evening switches. We recommend morning labs! Because there are fewer students your TAs wont be overworked, and therefore they'll be much happier to help. If you already have a project partner in mind, the two of you must be in the same lab. |
Newsgroup |
The newsgroup for this course is ucb.class.cs150, it is availible from news.berkeley.edu. To get access from off campus you can use a unix newsreader (such as tin) from an instructional server, you may use webnews (see the links page) or you may use AUS (see the links page).
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Course Goals |
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Course Syllabus |
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Last Updated: 06/08/2004 by | [an error occurred while processing this directive] |
Greg Gibeling |