CS 150. Components and Design Techniques for
Three hours of lecture, one hour of discussion, and three
laboratory per week. Prerequisites: 61C, Electrical Engineering 40 or
building blocks and design methods to contruct synchronous digital
Alternative representations for digital systems. Bipolar TTL vs. MOS
implementation technologies. Standard logic (SSI, MSI) vs. programmable
(PLD, PGA). Finite state machine design. Digital computer building
case studies. Introduction to computer-aided design software. Formal
laboratories and substantial design project. Informal software
periodically throughout semester. (F,SP) Katz, Newton, Pister.
- Understand digital
logic at the gate and switch level including both combinational and
sequential logic elements.
clocking methodologies to manage information flow and preservation of
- Appreciate digital
logic specification methods and the compilation process that transforms
these into logic networks.
- Gain experience
with computer-aided design tools for implementation with programmable
- Appreciate the
advantages/disadvantages between hardware and software implementations
of a function.
R. H. Katz, G.
Borriello, Contemporary Logic Design, 2nd Ed., Pearson Prentice-Hall, Upper
River, NJ, 2005.
Logic Design, Second Edition
Labs 1-5: 15%
Midterms (2): 20%
Final Project (including project Checkpoints 1, 2, 3): 30%
Final Exam: 20%
Homework and Quiz Policy
Homework will be graded
on effort. They will be due in the homework box outside of 125 Cory before lab
lecture at 2:10P each Friday.
Quizzes based on homework
will be given each Thursday in lecture. No make-up quizzes!
Post/receive announcements, questions, and discussions on UseNet news group ucb.class.cs150. The
staff will be using Google Groups to view the newsgroup, so we recommend that
you do the same.
||EECS 150 Fall 2006