EECS 150 Components and Design Techniques for Digital Systems     λ beef
CS 150 Fall 2006

TTh 2:00-3:30PM
306 Soda Hall
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Catalog Description

CS 150. Components and Design Techniques for Digital Systems. (5) Three hours of lecture, one hour of discussion, and three hours of laboratory per week. Prerequisites: 61C, Electrical Engineering 40 or 42. Basic building blocks and design methods to contruct synchronous digital systems. Alternative representations for digital systems. Bipolar TTL vs. MOS implementation technologies. Standard logic (SSI, MSI) vs. programmable logic (PLD, PGA). Finite state machine design. Digital computer building blocks as case studies. Introduction to computer-aided design software. Formal hardware laboratories and substantial design project. Informal software laboratory periodically throughout semester. (F,SP) Katz, Newton, Pister.

Course Goals

Course Textbook

R. H. Katz, G. Borriello, Contemporary Logic Design, 2nd Ed., Pearson Prentice-Hall, Upper Saddle River, NJ, 2005.

CLD 2nd Edition
Contemporary Logic Design, Second Edition

Course Grading

Homework: 10%
Quizzes: 5%
Labs 1-5: 15%
Midterms (2): 20%
Final Project (including project Checkpoints 1, 2, 3): 30%
Final Exam: 20%

Project Breakdown


Homework and Quiz Policy

Homework will be graded on effort. They will be due in the homework box outside of 125 Cory before lab lecture at 2:10P each Friday.

Quizzes based on homework will be given each Thursday in lecture. No make-up quizzes!

Public Discussion

Post/receive announcements, questions, and discussions on UseNet news group ucb.class.cs150. The staff will be using Google Groups to view the newsgroup, so we recommend that you do the same.

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UC Berkeley http://www-inst.eecs.berkeley.edu/~cs150/ EECS 150 Fall 2006