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EE243 Advanced IC Processing and Layout

Spring 2012 Course Information

This course starts with a generic overview of the CMOS fabrication sequence, key technology modules, and processing limitations and issues.

Front-end of the line (FEOL) processes: mechanisms and models for implantation, oxidation, diffusion, and substrate engineering.

Patterning: advanced models for optical image formation and resolution enhancement, resist response, defect printability, inspection, and nm-scale printing.

Back end of the line (BEOL) processes include deposition and etching (PVD,CVD, ALD, Epi, RIE, ALE), CMP, metallization, and heterogeneous integration of microsystems.

Contemporary issues such as gate stack engineering, strain engineering, and nonplanar devices (FINFET) will be used as case studies throughout the course. Extension of these process modules for displays, MEMS, Photovoltaics, and Nanotechnology will also be discussed.

The last 3 weeks cover basic statistical process control (SPC) and design of experiments (DOE) as used to support high yield manufacturing.

Course Materials

The materials used in this course have been co-developed with Professors Andy Neureuther and Costas Spanos. Notes for each lecture and some reading materials will be distributed to class participants via BSpace.

Required Textbooks:

Plummer, Deal and Griffin, 'Silicon VLSI Technology: Fundamentals, Practice and Modeling', 1st Edition (2000), Prentice Hall. 

SPC and DOE - Spanos and May. ‘Fundamentals of Sermiconductor Manufacturing and Process Control’ Chapters 4, 6 and 7( pdf reprints will be available to all enrolled students)

Homework

Homework assignments will be posted on the class webpage on Tuesdays and are due 10 days after (Fridays). Homework can be submitted electronically to the dropbox of Bspace (https://bspace.berkeley.edu/) in pdf (preferred) ,WORD, or jpeg formats. All graded homework will be returned to your dropbox in pdf format.

Hardcopies of homework will also be accepted in Cory 513 (BY SLIDING THEM UNDER THE DOOR) . The lowest score of the homework set will not count towards the course grade.

Term Project

A term project related to state-of-the-art technologies. The project can critique the pros and cons of an emerging technology; provide engineering design data and models; or apply a technology to novel situations. The use of TCAD tools or SPC methods are highly encouraged in these investigations. A short (10 min) web based presentation to class is required near the end of the semester.

Exam Schedule:

Midterm: About 8th Week of class, 2-hr exam

Final Exam: 3-hr exam

Grading Policy: Homework and Class Participation: 25% Project: 25% Midterm: 25% Final Exam: 25%

The lowest 2 HW scores will not count towards your overall course grade.

Last updated  1/3/2012

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