Welcome to the Fall 2009 CS250 web page. More details to follow.
|1||Thu Aug 27||JW||
Lecture 1: Course Introduction: overview of course material
and relation to other courses. Overview of course structure and
student requirements. Description of project.
VLSI Introduction: IC Fabrication, foundry model, chip-level alternatives: ASIC, FPGAs, full-custom, gate-array, via-programmable.
Quick tool flow overview. Lecture slides.
Lab 1 out
UPDATED once more!! See the News page!!
Lab 1 (Version 092509a)
|Fri Aug 28||YL||Section 1: Lab 1: Tool Flow Overview. Section slides.|
|2||Tue Sep 1||KA||
Lecture 2: RTL and other design representations.
Design methodology for good design. Unit-transaction modeling (UTL) & RTL.
Architecture versus uarchitecture.
Verilog and Synthesis: How to code verilog for desired results, Logic synthesis tools and how they work. Lecture slides.
|Thu Sep 3||JL||Lecture 3: Design Verification: Unit testing, random tests, regression testing, testing of FSMs. Dynamic verification tools (simulation and emulation). Lecture slides.|
|Fri Sep 4||YL||Section 2: Repository structure, test harnesses. Using revision control systems, test benches and environments. Section slides.|
|3||Tue Sep 8||JW||Lecture 4: Timing: Circuit and wire delay modeling and logical effort. Circuit level timing closure. Static timing tools. Lecture slides.||
Lab 2 out
Lab 2 (Version 092509a)
|Thu Sep 10||JL||Lecture 5: Power: energy and power, power consumption mechanisms, power modeling and power aware design overview. Power analysis tools. Lecture slides.||
Lab 1 due (11:00 AM)
|Fri Sep 11||YL||Section: Lab 2, SMIPS RTL Implementation and Synthesis Section slides.|
|4||Tue Sep 15||KA||Lecture 6: Project details, Infinicore Architecture. Lecture slides.|
|Thu Sep 17||KA||Lecture 7: Project Details and Decomposition. Creating groups.|
|Fri Sep 18||YL||Section: Optimizing your Register File and ALU. Section slides.|
|5||Tue Sep 22||JL/JW||Lecture 8: Floorplanning: Macroblock placement, Power/clock distribution and routing. Physical synthesis (back-end) tools (PPR). Power grid tools. Clock-tree synthesis. Formal verification, OPC/GDRC, VLS. Fill rules, antenna violations. Show how fab process leads to design rules. Chip architecture/layout examples: Microprocessors, FPGAs, SOC concepts. Lecture slides.|
|Thu Sep 24||JL/JW||Lecture 9: Floorplanning: Macroblock placement, Power/clock distribution and routing. Physical synthesis (back-end) tools (PPR). Power grid tools. Clock-tree synthesis. Formal verification, OPC/GDRC, VLS. Fill rules, antenna violations. Show how fab process leads to design rules. Chip architecture/layout examples: Microprocessors, FPGAs, SOC concepts. Lecture slides.||
Lab 2 due (before class)
Lab 3 out
Lab 3 (Version 092509a)
|Fri Sep 25||YL||Section: Lab 3: Backend tools (P+R), back annotation, timing/power analysis tools. Section slides.|
|6||Tue Sep 29||JW||Lecture 10: Design Blocks I. SRAM (logic/circuit/layout). Lecture slides.|
|Thu Oct 1||JW/JL||Lecture 11: Design Blocks II. PLA/ROM, structured datapath, switches, DRAM. Lecture slides.|
|Fri Oct 2||YL||Section: Lab 3 updates. Clock gating. Project group discussions. Section slides.|
|7||Tue Oct 6||KA||Lecture 12: Microarchitecture and RTL Optimization: retiming, pipelining, exploiting parallelism and associated PAT (power/area/timing) tradeoffs.|
|Thu Oct 8||JW||Off-chip memory - DDR interfaces, SERDES, etc. Design for Test: Scan and ATPG, BIST, (JTAG). Other DFx (x=manufacturing, ..). Scan chain insertion. Lecture slides.||Project Proposal due|
|Fri Oct 9||YL||Office hours (2-4pm)||Lab 3 due (12:30 PM)|
|8||Tue Oct 13||All||Group meetings (310 SODA): Review initial proposal.|
|Thu Oct 15||All||Group meetings (606 SODA): Review initial proposal.|
|Fri Oct 16||YL||Office hours (1-3pm)|
|9||Tue Oct 20||All||Paper Discussions paper1 paper2|
|Thu Oct 22||All||Paper Discussions paper|
|Fri Oct 23||YL||Office hours (2-4pm)|
|10||Tue Oct 27||All||Group meetings (310 SODA): Review functional model, test harness.|
|Thu Oct 29||All||Group meetings (606 SODA): Review functional model, test harness.|
|Fri Oct 30||YL||Office hours (2-4pm)|
|11||Tue Nov 3||All||Paper Discussions paper1 paper2 paper3|
|Thu Nov 5||All||Paper Discussions paper optional paper 1 optional paper 2|
|Fri Nov 6||YL||Office hours (2-4pm)|
|12||Tue Nov 10||All||Group meetings (310 SODA): Review initial microarchitecture design results.|
|Thu Nov 12||All||Group meetings (606 SODA): Review initial microarchitecture design results.|
|Fri Nov 13||YL||Office hours (2-4pm)|
|13||Tue Nov 17||All||Paper Discussions paper1 paper2|
|Thu Nov 19||All||Paper Discussions paper1 paper2|
|Fri Nov 20||YL||Office hours (2-4pm)|
|14||Tue Nov 24||All||Paper Discussions full paper1 - read the "Papers" page for directions. extracted paper1 paper2|
|Thu Nov 26||Thanksgiving|
|Fri Nov 27||Thanksgiving|
|15||Tue Dec 1||All||Group meetings (310 SODA): Review design space exploration results.|
|Thu Dec 3||All||Group meetings (606 SODA): Review design space exploration results.|
|Fri Dec 4||No Section|
|16||Tue Dec 8||All||Project Presentations (all day)|
|17||Mon Dec 14||Final Project Reports due at 9AM (no extensions)|