CA 714CA - Homework #0
Homework 0 is due on Thursday 1/25/02. This is not counted toward
your final grade. It is a review on prerequisite topics. You
should still turn in the homework to familiarize yourself with the homework
turn in procedure.
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List the following 5 stages of the MIPS processor in order from beginning
to end. Then briefly describe the function performed in each stage.
memory
access
decode
execute
write back
fetch
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Write after write (WAW), write after read (WAR), read after write (RAW)
are three types of potential data hazards. Give example for each
in MIPS assembly code.
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Processor A has 3 types of instructions, memory access, integer operation,
and floating point operation. Memory access takes 2 cycles each.
Integer operation takes 1 cycle each. Floating point takes 3 cycles
each. Program X compile for processor A has 30% memory access instructions,
50% integer operation instructions, and 20% floating point operation instructions.
What is the cycle per instruction (CPI) for processor A running program
X.
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Describe the following types of misses in cache. Describe how the
block size, associativity, and overall size of the cache affect each type
of miss.
Compulsory
Capacity
Conflict