NTU 6341 / EECS 141

Digital Integrated Circuits

Fall 2007

ANNOUNCEMENTS:

(11/28/07) Homework #6 and #7 is already available. See the Homework page.

(11/19/07) Homework #5 is already available. See the Homework page.

(10/14/07) Homework #4 is already available. See the Homework page.

(10/01/07) Homework #3 is already available. See the Homework page.

(09/17/07) Homework #2 is already available. See the Homework page.

(09/14/07)The website is up. Check here often for updates.

(09/04/07) First conference call is on Thursday (09/13/07) at 3:45 pm PT.

 

DESCRIPTION:

This course is an introduction to digital integrated circuits. The material will cover CMOS devices and manufacturing technology along with CMOS inverters and gates. Other topics include propagation delay, noise margins, power dissipation, and regenerative logic circuits. We will look at various design styles and architectures as well as the issues that designers must face, such as technology scaling and the impact of interconnect. Examples presented in class include arithmetic circuits, semiconductor memories, and other novel circuits.

The course will start with a detailed description and analysis of the core digital design block, the inverter. Implementations in CMOS will be discussed. Next, the design of more complex combinational gates such as NAND, NOR and XOR gates will be discussed, looking at optimizing the speed, area, and/or power. The learned techniques will be applied on more evolved designs such as adders and multipliers. The influence of interconnect parasitics on circuit performance and approaches to cope with them are treated in detail. Substantial attention will then be devoted to sequential circuits, clocking approaches and memories. The course will be concluded with an examination of design methodologies. CAD Tools for layout, extraction, and simulation will be used for assignments, labs and projects.

 

INSTRUCTOR: Jan M. Rabaey

 

COURSE CONSULTANT:

Louis P. Alarcn

Email: lalarcon at eecs dot berkeley dot edu

Office hours: Tuesdays/Thursdays 2-3 pm PT

Phone: (510) 642 5776

Fax: (510) 643 5877

 

CONTACT INFORMATION:

For course content and prerequisites, contact the course consultant. For information regarding registration, pricing or other administrative items, contact the CalVIEW office:

 

CALVIEW OFFICE

205 McLaughlin Hall

University of California, Berkeley

Berkeley, CA 94720

Phone: (510) 642-5776

Fax: (510) 643-5877

Email: ntu at coe dot berkeley dot edu

Web Page: www.coe.berkeley.edu/calview