"Reducing The Impact of Process Parameter Fluctuations on CMOS Digital Integrated Circuits"

EE241 Project, Spring 2003
Liang Teck Pang

Proposal

I propose to study the effects of process fluctuations on the performance of CMOS digital integrated circuits, and methods to reduce the variation in performance due to these fluctuations.

As CMOS transistor generation scales beyond 0.25um, process fluctuations are becoming more significant. The difficulty in obtaining precise control of the process results in statistical variations in process parameters. These parameters consist of the gate length, gate width, doping concentrations, doping profiles and oxide thickness. Of these, the gate length appears to have the most impact on transistor performance. In today's deep sub-micron era, threshold voltage is increasingly dependant on the gate length due to increasing short channel effects. Variation in threshold voltage directly affects transistor delay and leakage power . In order to manufacture integrated circuits with a good yield, present methodology adopts a pessimistic approach whereby all the circuits have to pass the timing analysis in the worst case process corners. This method is wasteful on resources. As process fluctuations increase, scaling from one technology to the next will not introduce as much performance enhancement due to the overhead in requiring all transistors to operate in the worst case corners. This problem has emerged as a possible stumbling block to Moore's law.

A few suggestions have been put forth to counter this obstacle[2,3]. In the quest for low leakage power, many techniques for controlling the threshold voltage using body biasing have been developed[4,5,6]. It has also been noted that, to use a low supply voltage, it is also imperative to have a good control of the threshold voltage[4]. These low power interests have resulted in many novel body biasing schemes. A solution to the problem of process fluctuations would be to use substrate biasing to control the threshold voltage. This idea has been implemented in[1] to eliminate die-to-die variation. The result is very promising as it is possible to bring all dies to the same speed.

In this project, I will study the effects of scaling on performance fluctuations and investigate the effectiveness of the method of substrate biasing in solving the problem. I will also explore the use of other methods to reduce within-die fluctuations such as controlling the number of pipeline stages and estimating the area of control of a replica critical path. Finally, I will suggest practical implementations of some of the methods analyzed.

Midterm Report (pdf)

Project Presentation (ppt)

Project Report (doc)

 

 

References:

  1. J. Tschanz et al, "Adaptive Body Bias for reducing impacts of die-to-die and within-die parameter variations on microprocessor frequency and leakage", IEEE JSSC, vol. 37, no. 11, Nov 2002
  2. S. Narendra et al, "Impact of using adaptive body bias to compensate die-to-die Vt variation on within-die Vt variation", Low Power Electronics and Design, 1999. Proceedings. 1999 International Symposium on , 1999, Page(s): 229 -232
  3. K. Bowman et al, "Impact of Die-to-Die and Within-die parameter fluctuations on the maximum clock frequency distribution for Gigascale integration", IEEE JSSC, vol. 37, no. 2, Feb 2002
  4. T. Kuroda et al, "A 0.9V, 150MHz, 10mW, 4mm2 , 2-D Discrete Cosine Transform Core Processor with Variable Threshold-Voltage (VT) Scheme," IEEE JSSC, vol. 31, no.11, Nov 1996
  5. M. Miyazaki et al, "A 1.2 GIPS/W Microprocessor Using Speed-Adaptive Threshold-Voltage CMOS with forward bias", IEEE JSSC, vol. 37, no. 2, Feb 2002
  6. A. Keshavarzi et al, "Effectiveness of reverse body bias for leakage control in scaled dual Vt CMOS ICs", Low Power Electronics and Design, International Symposium on, 2001. , 2001
    Page(s): 207 -212