Introduction to Digital Design and Integrated Circuits
Letures, Labs, Office Hours
Lectures | Tue, Thu | 3:30 pm - 5:00 pm | 540AB Cory | John Wawrzynek |
Discussion | Fri | 9:00 am - 10:00 am | 521 Cory | Chris Yarp |
ASIC Lab | Wed | 5:00 pm - 8:00 pm | 125 Cory | Arya Reais-Parsi |
FPGA Labs | Wed | 2:00 pm - 5:00 pm | 125 Cory | Chris Yarp |
Thu | 11:00 am - 2:00 pm | 125 Cory | Chris Yarp | |
Office Hours | Thu | 2:30 pm - 3:30 pm | 631 Soda | John Wawrzynek |
Tue | 2:30 pm - 3:30 pm | 125 Cory | Chris Yarp | |
Wed | 12:45 pm - 1:45 pm | 125 Cory | Chris Yarp | |
Fri | 11:00 am - 12:00 pm | 258 Cory | Arya Reais-Parsi |
Discussions, Homework
- Ask questions on our Piazza forum.
- Homeworks will be posted as links in the outline below and announced on Piazza. Please submit completed homework via Gradescope. See Piazza for the entry code.
Course Outline
Week | Date | Lecture Topic | Discussion | ASIC Lab | FPGA Lab | Homework |
---|---|---|---|---|---|---|
1 | 1/22 | Class Organization & Introduction to Course Content slides | Lab 1 (Getting Around the Compute Environment) | Lab 1 (Setup Accounts, Verilog Intro, FPGA Basics) | ||
1/24 | Design Alternatives & ASIC Flow slides | Discus. 1 | HW1 Solution | |||
2 | 1/29 | Verilog Part 1 slides | Lab 2 (Verilog Simulation) | Lab 2 (FPGA Toolchain, FPGA Mapping, Tone Gen) | ||
1/31 | Verilog Part 1 continued | Discus. 2 | HW2 Solution | |||
3 | 2/5 | Verilog Part 2 - Sequential Elements slides | Lab 3 (Logic Synthesis) | Lab 3 (Simulation, ROM-based music playback) | ||
2/7 | FPGA Architecture slides | Discus. 3 | HW3 Solution | |||
4 | 2/12 | Boolean Algebra slides | Lab 4 (Floorplanning, Placement and Power Routing) | Lab 4 (Synchronization, Debouncer, Resets, FSM) | ||
2/14 | Finite State Machines slides | Discus. 4 | HW4 Solution | |||
5 | 2/19 | CMOS Devices and Processing slides | Lab 5 (CTS and Routing) | Lab 5 (Serial I/O, building UART transmitter) | ||
2/21 | CMOS Circuits (CL, State Elements, Wires) slides | Discus. 5 | HW5 Solution | |||
6 | 2/26 | Circuit Timing, part 1 slides | Lab 6 (Power and Timing Verification) | Lab 6 (FIFOs, UART Piano) | ||
2/28 | Circuit Timing, part 2 slides | Discus. 6 | HW6 Solution | |||
7 | 3/5 | Power and Energy slides | Lab 7 (SRAM Integration) | Preliminary Project Specification Release | ||
3/7 | RISC-V Processor Implementation slides | Discus. 7 Handout | ||||
8 | 3/12 | Midterm 1 Review Exam Topics, slides | Project Released (Timeline overview) | Project Released (Subject to Change) | ||
3/14 | Midterm 6-9PM (in Soda 306 - HP Auditorium) - no class | |||||
9 | 3/19 | Accelerators slides | Project Checkpoint 1 | |||
3/21 | Memory Circuits slides | Discus. 8 Handout | ||||
10 | 3/26 | No classes (Spring Recess) | Project Checkpoint 1 | HW7 Solution | ||
3/28 | No classes (Spring Recess) | |||||
11 | 4/2 | Power/clock distribution slides | ||||
4/4 | Memory Blocks slides | Discus. 9 Handout | HW8 Solution | |||
12 | 4/9 | Parallalism and Design Optimization slides | Project Checkpoint 2 | Project Checkpoint 2 | ||
4/11 | Adders slides | Discus. 10 | HW9 Solution | |||
13 | 4/16 | Multipliers slides | Project Checkpoint 3 | |||
4/18 | High Level Synthesis and Deep Neural Nets slides | Discus. 11 | ||||
14 | 4/23 | More Multipliers, Counters, LFSRs, Shifters slides | ||||
4/25 | List Processor Example slides | Discus. 12 | HW10 Solution | |||
15 | 4/30 | Faults in ICs slides | Project Checkpoint 4 | Project Checkpoint 3, Interview | ||
5/2 | Wrap-up and Exam Review Exam Topics,slides | Discus. 13 Handout | ||||
RRR Week | No classes | Project Interview | Final Project Checkoff Logistics | |||
Exam Week | 5/17 | Final Exam 7–10PM (in Hearst Gym 251) | Project Report Due | Project Report Due |
Staff
John Wawrzynek | johnw at berkeley dot edu | |
Chris Yarp | cyarp at berkeley dot edu | |
Arya Reais-Parsi | aryap at berkeley dot edu | |
Prashanth Ganesh | prashanthcganesh at berkeley dot edu |
Homework Policy
Homework will be released on Fridays before midnight, and will be due on the Monday 10 days later. Homework will be challenging and graded for correctness.
Grading
Class
Participation | 10% |
Midterm Exam | 25% |
Problem Sets | 30% |
Final Exam | 35% |
ASIC Labs
Lab Reports | 37.5% |
Project | 62.5% |
FPGA Labs
Lab Checkoffs | 25% |
Project | 75% |
Cheating Policy
- If you turn in someone else’s work as if it were your own, you are guilty of cheating. This includes problem sets, answers on exams, lab exercise checks, project design, and any required course turn-in material.
- Also, if you knowingly aid in cheating, you are guilty.
- We have software that compares your submitted work to others.
- However, it is okay to discuss with others lab exercises and the project (obviously, okay to work with project partner). Okay to discuss homework with others. But everyone must turn in their own work.
- Do not post your work on public repositories like github (private o.k.)
- If we catch you cheating, you will get negative points on the assignment: It is better to not do the work than to cheat! If it is a midterm exam, final exam, or final project, you get an F in the class. All cases of cheating reported to the office of student conduct.