EE290B, Fall 2007
Advanced Topics in Solid State Devices
Tues & Thurs: 12:30 - 2:00 pm
299 Cory Hall
Graduate Student status
A prior course in Solid State Electronics
A prior course in Quantum Mechanics
Requirements for Credit:
There will be a Mid-Term Exam, but no Final Exam. A
Final term paper will be required, that accurately analyzes a given option for efficient
short-range communication on future chips. The Final Grade will be based on the
mid-term exam, and the term paper.
Optional Reference BooK:
Jasprit Singh, “Electronic and Optoelectronic Properties of
Semiconductor Structures”, (Cambridge University Press, 2003).
ISBN 0 521 82739 X
This book has valuable information on semiconductor band structure,
that is worth retaining for permanent reference.
Professor Eli Yablonovitch
267M Cory Hall
Phone: (510) 642-6821
Wednesday 1 - 3PM, 267M Cory Hall
Course Administrative Assistant:
253 Cory Hall
Phone: (510) 642-2384
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Welcome to EE290B
In this course we will analyze the major roadblocks standing in the path of further progress in digital nano-electronics. We start by acknowledging the culmination of conventional "critical-dimension" scaling in the semiconductor ITRS roadmap. Therefore it appears justified that there may emerge a new scaling paradigm based on power. Some limits on energy efficiency for logic operations, memory operations, and communications, will be derived. The apparent major obstacle appears to be the excess signal-to-noise ratio that is designed into conventional digital electronics.
This is dictated by the fact that the universal switch, the transistor, is thermally activated, and requires a high voltage >>kT/q~1Volt to operate well. On the other hand the wires in a circuit would have tolerable signal-to-noise ratio operating even at 1 mVolt. This manifests itself as a factor ~10^6 inefficiency in current digital electronics.
We will project some anticipated technical options that could eventually eliminate this million-fold factor:
1. solid-state switching devices, that operate in the milli-Volt regime.
2. nano-transistor options with steeper sub-threshold slope.
3. nano-optical links.
4. novel nano-scale impedance matching transformers, including plasmonics.
5. new forms of amplification using giant magneto-resistance, and other spintronic effects.
6. nano-mechanical switching elements that are capable of very low voltage operation.
7. low-temperature electronics.
8. electro-chemical switching elements.
The goal of the course is to anticipate which device option would most likely represent the future of digital electronics.
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- Please be prepared for makeup classes, owing to various scheduling problems.
- Hard copies of Lectures will be given in class.
- Click on this link to reach the main web site for EE290B at bSpace
- Office Hours for Wednesday, October 31st, have been changed to: Thursday, November 1st, 2:00 pm-4:00pm.
- Last class, Thursday, December 6, 2007.
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There will be a Mid-Term Exam, but no Final Exam. A Final term paper will be required, that accurately analyzes a given option for efficient short-range communication on future chips. The Final Grade will be based on the mid-term exam, and the term paper.
- Term Paper Topics
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Last updated November 1, 2007