Role of VHDL
In general, VHDL syntax is sufficient and probably not worth re-working.
In some cases VHDL goes too far.
- e.g. if(CLK'quiet for 4) A := B+1;
In some cases not far enough
- e.g. Synchronizing elements in dataflow view.
We need a Policy-of-Use for VHDL-based synthesis
- In-progress within the industry (e.g. Synopsys)
- NSF/DARPA group looking into it.
- International standards groups also working on some issues world wide (e.g. IEEE DATC).