Table of Contents
EE244: Design Technology for Integrated Circuits and Systems Outline Lecture 7.1
What is High-Level Synthesis?
Algorithms and Programs
Sequential Control-Flow Model
What is High-Level Synthesis?
What is High-Level Synthesis?
Representing the Synthesis Problem: The Conventional Approach
Representing the Synthesis Problem: An Alternative Approach
What is an Architecture?
What is an Architecture?
What is an Architecture?
Specification vs. Description
High-Level Synthesis
Converting Procedural Descriptions to a Dataflow-Oriented Representation
Complications to Dataflow Analysis
Complications to Dataflow Analysis
Complications to Dataflow Analysis
Conventional Steps in High-Level Synthesis
Components of a Conventional High-Level Synthesis Target
Parallelism, Pipelining, and Graph Folding
Maximally Parallel and Maximally Pipelined
Maximally Parallel, Minimum Control States
Widthwise Folding via Symbolic Dependencies
Parallelism, Pipelining, and Graph Folding
Maximally Pipelined: Storage Requirements
Sharing Storage
Effect of Scheduling on Interconnects
Approaches to Scheduling
As-Soon-As-Possible (ASAP) and As-Late-As-Possible (ALAP) Scheduling
Approaches to Scheduling
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Author: Richard Newton
Email: rnewton@ic.eecs.berkeley.edu
Home Page: http://www-inst.eecs.berkeley.edu/~ee244
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