EE244: Design Technology for Integrated Circuits and Systems Outline Lecture 3.2

9/16/97


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Table of Contents

EE244: Design Technology for Integrated Circuits and Systems Outline Lecture 3.2

Taxonomy of VLSI Routers

Maze Route: Lee Path Connection Algorithm

Line Probe: Hightower & Tabuchi

Line Search: Hightower & Tabuchi

Pattern Route: Soukup

Channel Routing

Routing Region Definition

Channel Routing

Channel Routing

Vertical Constraint Graph

Greedy Router: Rivest & Fiduccia

Greedy Router

Greedy Routing Example

Left-Edge Algorithm (LEA) (Hashimoto & Stevens)

Left-Edge Algorithm (LEA) (Hashimoto & Stevens)

“Merging of Nets” (Yoshimura & Kuh)

Merging of Nets

Merging of Nets: Example

Introducing Doglegs

Cyclic Constraints

YACR: Pattern Routing

 Author: Richard Newton

Email: rnewton@ic.eecs.berkeley.edu

Home Page: http://www-inst.eecs.berkeley.edu/~ee244