EECS 244 Computer-Aided Design of Integrated Circuits and Systems
Administrative Details
Goals of the Course
Design Technology
Semiconductor Industry Growth
Semiconductor Capital Investment
SIA/SRC 1994 National Technology Roadmap
Today’s Design Methodologies Will Not Scale Much Further
Chip Interconnect Systems
PPT Slide
Power as the Driver
Particular Function (e.g. MPEG)
Some Implications
Advanced CMOS Design Methodology
Representation as an Aid in Decision Support
Beyond Hierarchy
Abstractions for Collaboration
Simplified Model of Design
Structured Custom Chip Layout
Cell-Based Design Styles
ASIC Design Starts
Standard Cell Layout
Standard Cells vs. Gate Array
Layout Abstractions for Cell-Based Design
Channeled Gate Array
Placement & Routing
SOC in 1996
Capacitance of Crossing Lines
Other Near-Term Micro-Architectures
SOC Challenge
Single-Chip Silicon Implementation Styles
Integrated Head-Mounted Display
Summary
Email: rnewton@ic.eecs.berkeley.edu
Home Page: http://www-inst.eecs.berkeley.edu/~ee244