EE244 Homework #2 (Extra-Lite!)
The costs that we are concerned with are delay in the
circuit. The delay model that we have in this assignment is
oversimplified for your convenience. Wires will have a cost/unit
length depending on which layer they are located on. Vias will have
a cost/instance. In practice, numerous tricks are played to
overcome resistance in long wires or vias, is quadratic for long wires
and is also significant in vias, but in practice there are a number of
ways to subvert this.
These costs should be specified by the user (via a dialog
box), and should have the following defaults:
Layer 0: 1 cost/unit length
Your algorithm should have two modes:
Layer 1: 1 cost/unit length
Via: 5 cost/instance
Optimize for average cost of all nets
Optimize for maximum cost of all nets (try to minimize
The histogram which displays your results should have
two axes. The X axis should be net costs, the Y axis should be number
of nets which have that particular cost.
Here are a number of new dot files representing challenging
channels to route. It has not been decided which circuits will be
required for the homework.
Many thanks to Dr. Hiroshi Murata of UC Berkeley and Professor
Atsushi Takahashi of Tokyo Institute of Science and Technology for providing
Your turnin should consist of the following items:
Please make an HTML page which links all of these items,
and send the URL link in an e-mail message to firstname.lastname@example.org
with the subject "ee244 hw1 turnin".
An applet which demonstrates your algorithm.
This will be run remotely and should perform reasonably well.
A short description of the algorithms and data structures
you implemented. In particular, how did you modify your algorithm
from homework 1 to optimize the cost?
A short textual analysis of your algorithm's performance.
What does the distribution you've plotted mean about the algorithm?
Michael Shilman <email@example.com>