EE244 Fall 1997
Below is a list of topics to be covered and
an approximate order. The exact material and emphasis will be determined
by student interests and needs as the course progresses. All preliminary
examination material will be covered in detail.
Electronic Systems Design
Physical Design Styles and Evolution
Full Custom Design, Cell-based Design, Structured Custom Design
Impact of Deep Sub-Micron Technologies
Computational Issues in Physical Design
General Issues, Solution time, Problem size
Data Structures for Physical Design
Role of Computational Geometry
Representing geometry & its characteristics
Representing the plane: Grids, tessellation, etc.
Bins and Trees
Logical connectivity & Netlists
Integrating with physical information
Metrics for Physical Design: Distance, Connectivity, Net length, Density,
Delay (net, path), Power Dissipation
Models for physical design
Elmore Time Constant
Statistical Characteristics Of Wiring
Rent's Rule, Donath & Heller
Power Dissipation Approximations
Quality metrics & constraints
Greedy, Kernighan-Lin, Fiduccia-Mattheyses, Stochastic approaches
Modern approaches and new directions
What is floorplanning?
Tutte's approach, Clustering, Analytical, Simulated annealing
Component Placement or Assignment
What is the placement problem?
Placement vs. Assignment
Placement quality and constraints
Partition-based, Min-cut, Force-directed approaches, Quadratic assignment,
Problem definition & classification of approaches
Routing region definition and ordering
Breadth-first search (maze), Soukup's modification, Steiner-tree-based
algorithms, Integer linear programming, Simulated annealing
Problem definition: layers, vias, etc.
Generalized routing: Grid-based, "Gridless"
Channel routing: Greedy, LEA, Yoshimura-Kuh, Dogleg, YACR2
Switchbox, Rip-up & re-route
Cleanup & compaction
1-D Approaches, Zone Refining, 2-D Compaction
Module Generation and Silicon Compilation
Introduction to Layout Styles
Datapath generation, parameterized layout, Weinberger Arrays & Gate
PLA folding: Simple and Constrained
Synthetic library generation
CMOS static cell generation
TILOS approach, Lagrangian Multiplier Approaches, Marple's approach, Convex
Detailed Layout Analysis and Verification
Solving for IR-drops, clock skew, etc.
Hierarchical layout analysis
Incremental layout analysis
Netlist comparison: Graph matching
Combinatorial Complexity and General Search
Layout of graphs
Generalized search, rational search
Utility, Branch and Bound, Probabilistic Branch and Bound, Other approaches
Bayesnets, more to come!
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