For problem 2 and 3, assume an n+ gate for the capacitor. Also change the flatband voltage (V_FB) to -1V for problem 2. Please check the newsgroup for more information and hints.
In the solutions handed out in class on Wed 26 Sept, the answer given for problem 2b is incorrect. This answer does not account for the reverse-biased pn-junction in the active-to-substrate region, and so to correct this, the answer in the solutions should be divided by a factor as given in equation 3.80 of the text. The online solutions will reflect this change when they get posted. Sorry for the confusion.
Lab 3 will be a formal lab. Please read the lab manual and be well prepared with your Prelab before attending your lab section. A color version of Lab 3 procedure is posted here.
Supplemental Part for lab 3 is posted.Supplemental Part for lab 4 is posted.
An outline for your formal lab report is also posted.