References

 [Pat1] David Patterson, et al., "A Case for Intelligent RAM", IEEE Micro, 1992. pp 34-44..

[Pat2] David Patterson, et al., "Intelligent RAM (IRAM): the Industrial Setting, Applications, and Architectures", 1992.

[Got1] Gensuke Goto, et al., "A 54x54-b Regularly Structured Tree Multiplier", IEEE Journal of Solid-State Circuits, 1992. pp 1229-1236.

[Lem1] Carl Lemonds, "A High Throughput 16 by 16 Bit Multiplier for DSP Cores", IEEE International Symposium on Circuits and Systems, 1996. pp 477-480.

[Fad1] Jalil Fadavi-Ardekani, "M x N Booth Encoded Multiplier Generator Using Optimized Wallace Trees", IEEE Transactions on Very Large Scale Integration, 1993. pp 120-125.

[Mad1] Philip E. Madrid, et al., "Modified Booth Algorithm for High Radix Multiplication", IEEE International Conference on Computer Design: VLSI in Computers and Processor, 1992. pp 118-121.

[Che1] Brian S. Cherkauer; Eby G. Friedman, "A Hybrid Radix-4/Radix-8 Low Power, High Speed Multiplier Architecture for Wide Bit Widths", IEEE International Symposium on Circuits and Systems, 1996. pp 53-56.

[Bre1] Luca Breveglieri, et al., "Column Compression Pipelined Multipliers", Proceedings. The International Conference on Application Specific Array Processors, 1995. pp 93-103.

[Tak1] Toshinari Takayanagi, et al., "350 MHz Time-Multiplexed 8-Port SRAM and Word-Size Variable Multiplier for Multimedia DSP", IEEE Solid-State Circuits Conference, 1996. pp 150-151, 434.

[Mat1] Masataka Matsui and James B. Burr, "A Low-Voltage 32 x 32-Bit Multiplier in Dynamic Differential Logic", IEEE Symposium on Low Power Electronics, 1995. pp 34-35.

[Mil1] Brian Millar and Philip Madrid., "A Fast Hybrid Multiplier Combining Booth and Wallace/Dadda Algorithms", Proceedings of the 35th Midwest Symposium on Circuits and Systems, 1992. pp 158-165.