Power/Cycle Time/Area Summary

  • Basic Assumption

    (1) Technology : 0.35um CMOS process
    (2) Operating Voltage(Variable Threshold Voltage) : 2.5 V (Vt=0.5V) 2.0 V (Vt=0.4V) 1.5 V (Vt=0.3V) 1.0 V (Vt=0.2V)
    (3) Operating Temperature : 25 C
    (4) Circuit : Dual-Rail Domino Transistor vs. Double Pass-Transistor
    (5) Worst Case Comparison : 64 bit Floating Point Logic

  • Power/Cycle Time/Area Performance Analysis Table 25 : Comparison with Various Low Power Design ( Limited on the worst case of Multiplication 64bit Floating Point )

    0.35uM Process
    64bit Floating Point

    Square Ratio
    Dual-Rail Domino Logic
    2.5 V

    Natural Ratio
    Dual-Rail Domino Logic
    2.5 V

    Enhanced Ratio
    Dual-Rail Domino Logic
    2.5 V

    Enhanced Ratio
    Double Pass Transistor
    2.5 V

    Enhanced Ratio
    Double Pass Transistor
    2.0 V

    Enhanced Ratio
    Double Pass Transistor
    1.5 V

    Enhanced Ratio
    Double Pass Transistor
    1.0 V

    Worst Case Power (FP64)

    3354.66 mW

    3319.09 mW

    1696.86 mW

    563.58 mW

    380.86 mW

    257.84 mW

    116.21mW

    Relative Worst Case Power (FP64)

    101.07

    100.00

    51.12

    16.98

    11.47

    7.77

    3.50

    Worst Case Cycle Time (FP64)

    5 cycles

    5 cycles

    3 cycles

    4 cycles

    5 cycles

    5 cycles

    6 cycles

    Channel Width Estimation

    1103.11 mm

    986.22 mm

    774.23 mm

    456.23 mm

    456.23 mm

    456.23 mm

    456.23 mm

    Area Estimation

    3.86 mm2

    3.45 mm2

    2.71 mm2

    1.60 mm2

    1.60 mm2

    1.60 mm2

    1.60 mm2

    relative Area Estimation

    1.12

    1.00

    0.79

    0.46

    0.46

    0.46

    0.46

    [ TABLE 25 ]