Having determined the power, area, and throughput of the initial architecture, it was deemed necessary to curb the tremendous power consumption of the design, even if area and latency might be compromised. The "square" ratio design was seen to be a high power consumer, this was dropped for the lower power "natural" ratio. This reduced the number of needed input registers to only eight (8), 16 Bit registers. The "natural" ratio also reduced the complexity and muxing of the Sailboat Allocation, also reducing power.

Consuming 70-90% of the power and over 50% of the area, the multiplier was the most prominant sore spot in the design. The initial booth multiplier was replaced by the straight forward wallace tree compressor followed by a single 16 Bit Adder. Partial products for 32 & 64 Bit multiplications would bypass the 16 Bit adder, saving considerable power, area, and time. This scheme was also followed for 32 Bit multiplication as well. The final low power Tri-Multiplier (Figure 4) reduced power by a factor of 6 and area by a factor of 2.5 without changing the process technology.

Figure 4