Current advances in combined DRAM and combinational logic fabrication has allowed the development of microprocessors with dynamic RAM on chip. Because of the high bandwidth delivered by such proposed schemes [Pat1], a microprocessor must be chosen that can handle high bandwidth at low power. Vector architectures have been proposed to fulfilling both of these needs. VIRAM is a proposed such architecture that also seeks to bridge the gap between DSP processors and general purpose processors [Pat2], citing that there will be an increased demand for graphics, speech recognition, and wireless digital communication. Such compounding of requirements places a heavy emphasis of the multiplier design.

VIRAM requires a multiplier that can perform multiplication on three different data types: fixed point, floating point, and integer. Because of the trend to integrate floating-point and integer units [Got1], it was deemed necessary to combine all three of the different multiplications into one unit as well. In conjunction to the above requirement, the "tri-multiplier" would have to be able to produce variable width products, namely 64 bit, 32 bit, and 16 bit. Focusing on meeting the requirements of a pipelined, variable width tri-multiplier, power consumption was considered a secondary concern to be reduced after an initial architecture drafted.