| Modern times have merged design methodologies behind general purpose and DSP processors. Merging of DRAM and combinational logic has also brought forth the reintroduction of vector processors that satisfy the high bandwidth provided by on-chip memory. Specific to the IRAM case, vector processors must interact smoothly with three given data types. This requires the multiplier units to perform fixed point (DSP) multiplication, while keeping the ability to perform regular floating point and integer functionality. To satisfy these conditions, our research focuses on combination of three multipliers into a single pipelined "variable width tri-multiplier" while adhering to strict power requirements. Current technology (0.35 uM Process, Double Pass Transitor Logic, 2.5V operation) allows for the Worst Case 563.58 mW multiplier (64 Bit Floating Point) with 1.60 mM 2 area, while future technology (0.35 uM Process, Double Pass Transitor Logic, 1.0V operation) might allow for 0.2V Threshold Voltage, reducing power to only the Worst Case 116.21 mW (64 Bit Floating Point). |