Having to have a pipelined structure, many possible schemes were found and a high speed 16 bit multiplier was chosen [Lem1]. This multiplier was chosen because of the need for a 16 bit design which would allow for 64 & 32 bit calculation by 16/4x16 bit partial production addition (figure 1).

Figure 1

Another important consideration to decide on was either to use the Natural scaling (1/2/4) or the Squared scaling (1/4/16) ratio (figure 2).

Figure 2

Both of these are possible due to the creation of 16 partial products for 64 bit multiplication. The design considerations and trade offs of different schemes are described below. After the initial design was completed, reduction of power consumption was deemed vital before possible consideration in the VIRAM design.

The final major design consideration to take into account was the correct calculation of 32 & 64 Bit numbers by addition of unsigned 16 Bit partial products. Signed 16 Bit multiplication is also necessary for 16 Bit multiplication, therefore, conversions from signed to unsigned multiplication must be perfomed. For the architectures explored, 16 Bit, 32 Bit, and 64 Bit conversions must be performed.