Cycle Time Analysis I : Natural Ratio & Square Ratio

Basic Assumption

(1) Technology : 0.35um CMOS process
(2) Operating Voltage : 2.5 V
(3) Operating Temperature : 25 C
(4) Circuit : Dual-Rail Domino Logic
(5) 16 bit Multiplier : The radix-4 Booth Algorithm
(6) 6 subcycles : 1 main cycle is divided by 6 subcycles

Cycle Time Estimation Method

(1) The Cycle Time calculation is based on the paper, Carl Lemonds, "A High Throughput 16 by 16 Bit Multiplier for DSP Cores", IEEE International Symposium on Circuits and Systems, 1996. p479.
(2) Transformation of Power Calculation in Table III of the paper, Carl Lemonds

Cycle Time

@1200 MHz

Sail Boat Allocation

1 subcycle

16bit Multiplication

9 subcycles

Pipelined 16bit Multiplication Latency

3 subcycles

48bit Wallace Tree Compression

1 subcycle

48bit Addition

4 subcycles

32bit FP Conversion

4 subcycles

96bit Wallace Tree Compression

1 subcycle

96 bit Addition

5 subcycles

64 bit FP Conversion

5 subcycles

[ TABLE 7 ]


(3) Cycle Time Table 8 : Natural Ratio & Square Ratio

Cycle Time

mult16 FIX/INT

mult32 FIX/INT

mult32 FP

mult64 FIX/INT

mult64 FP

Sail Boat Allocation

1 subcycle

1 subcycle

1 subcycle

1 subcycle

1 subcycle

16bit Multiplication

9 subcycles

9 subcycles

9 subcycles

9 subcycles

9 subcycles

Pipelined 16bit Multiplication Latency

3 subcycles

3 subcycles

3 subcycles

3 subcycles

3 subcycles

48bit Wallace Tree Compression

N/A

1 subcycle

1 subcycle

1 subcycle

1 subcycle

48bit Addition

N/A

4 subcycles

4 subcycles

4 subcycles

4 subcycles

32bit FP Conversion

N/A

N/A

4 subcycles

N/A

N/A

96bit Wallace Tree Compression

N/A

N/A

N/A

1 subcycle

1 subcycle

96bit Addition

N/A

N/A

N/A

5 subcycles

5 subcycles

96 bit FP Conversion

N/A

N/A

N/A

N/A

5 subcycle

Total Subcycles

13 subcycles

18 subcycles

22 subcycles

24 subcycles

29 subcycles

Total Main Cycles

3 cycles

3 cycles

4 cycles

4 cycles

5 cycles

[ TABLE 8 ]