Upon completion of preliminary architecture for the VIRAM tri-multiplier, much insight has been gained about multiplier design and conforming such to the VIRAM requirements. The initial tri-multiplier design was cumbersome in all respects except throughput. The square ratio multiplication scheme could produce 2-4X the output of the natural ratio, but the cost in power is too substantial. After power analysis of the initial multiplier, it was gleamed that over 70% of the power was in the 16-bit multiplier, this had to be reduced. Use of lower power logic styles (double pass transistor vs. dual rail dynamic) and a slower clock cycle reduced power greatly (3X). Further improvements were gained by architectural changes by removing components that are not used in the natural ratio scheme and by bypassing additions when possible. All these changes consider, power was reduced to 563.58 mW with use of the same technology. By suggesting a possible roadmap for the future, power can be further reduced to 116 mW by using the Enhanced Natural Ratio (Double Pass Transistor @1.0V). Although latency was not a major issue for our design, we still achieved a max cycle delay of four (4) cycles for the Enhanced Natural Ratio (Double Pass Transistor @2.5V) . Integration of the design into the VIRAM architecture will require few changes or requirements. The only foreseeable requirement of VIRAM is a DLL to produce the multiplication of the 200 MHz clock cycle to the needed 800 MHz interpipelined frequency. With the addition of the tri-multiplier to VIRAM design, the VIRAM vector processors will be able to keep up with the high bandwidth delivered by the on-chip RAM. This high bandwidth capability will also allow the VIRAM to handle the real time constraints placed on DSP applications.