Area Analysis III : Low Power Design Technology
|
Channel Width |
Dual-Rail Domino Logic |
Double Pass Transistor Logic |
|
16bit Multiplier |
111.064 mm |
65.447 mm |
|
Combinational Logic per 1 transistor |
1.832 um |
1.080 um |
|
Wallace Tree Compressor per 1 transistor |
5.217 um |
3.074 um |
|
Register per 1 transistor |
7.462 um |
4.397 um |
|
16bit Carry Look Ahead Adder |
8.760 mm |
5.162 mm |
|
32bit Carry Look Ahead Adder |
22.379 mm |
13.187 mm |
|
48bit Carry Look Ahead Adder |
38.736 mm |
22.826 mm |
|
64bit Carry Look Ahead Adder |
57.170 mm |
33.689 mm |
|
96bit Carry Look Ahead Adder |
98.957 mm |
58.313 mm |
|
128bit Carry Look Ahead Adder |
146.052 mm |
86.065 um |
[ TABLE 23 ]
(3) Area Table 24 : Variable Circuitry
|
Channel Width |
Natural Ratio |
Enhanced Natural Ratio |
Enhanced Natural Ratio |
|
Sail Boat Allocation |
104.03 mm |
104.03 mm |
61.30 mm |
|
16 bit Multiplier |
444.26 mm |
N/A |
N/A |
|
32 bit Wallace Tree |
N/A |
130.55 mm |
76.93 mm |
|
32 bit CLA Adder |
N/A |
22.38 mm |
13.19 mm |
|
48 bit Wallace Tree |
61.64 mm |
124.83 mm |
73.559 mm |
|
48 bit CLA Adder |
154.94 mm |
N/A |
N/A |
|
64 bit CLA Adder |
N/A |
114.34 mm |
67.38 mm |
|
32 bit FP Converter |
41.77 mm |
20.89 mm |
12.31 mm |
|
96 bit Wallace Tree |
30.54 mm |
61.08 mm |
35.99 mm |
|
96 bit CLA Adder |
98.96 mm |
N/A |
N/A |
|
128 bit CLA Adder |
N/A |
146.05 mm |
86.06 mm |
|
96 bit FP Converter |
26.68 mm |
26.68 mm |
15.72 mm |
|
Output Registers |
23.40 mm |
23.40 mm |
13.79 mm |
|
Total Channel Width |
986.22 mm |
774.23 mm |
456.23 mm |
|
relative Area |
100.00 |
78.50 |
46.26 |
[ TABLE 24 ]