Cheol-Woong Lee & Norman Walker's CS252 Project Report

Area Analysis II : Natural Ratio vs. Enhanced Natural Ratio

Basic Assumption

(1) Technology : 0.35um CMOS process
(2) Operating Voltage : 2.5 V
(3) Operating Temperature : 25 C
(4) Circuit : Dual-Rail Domino Logic
(5) 6 subcycles : 1 main cycle is divided by 6 subcycles
(6) 16 bit Multiplier : Wallace Tree + 32bit CLA Adder
(7) Architectural Change but No Change for Circuit and Process Technology

Area Estimation Method

(1) The Area calculation is based on the paper, Carl Lemonds, "A High Throughput 16 by 16 Bit Multiplier for DSP Cores", IEEE International Symposium on Circuits and Systems, 1996. p479.
(2) Transformation of Area Calculation in Table III of the paper, Carl Lemonds

Channel Width	@200 MHz
16bit Multiplier	111,064 um
Combinational Logic per 1 transistor	1.832 um
Wallace Tree Compressor per 1 transistor	5.217 um
Register per 1 transistor	7.462 um
16bit Carry Look Ahead Adder	8.760 mm
32bit Carry Look Ahead Adder	22.379 mm
48bit Carry Look Ahead Adder	38.736 mm
64bit Carry Look Ahead Adder	57.170 mm
96bit Carry Look Ahead Adder	98.957 mm
128bit Carry Look Ahead Adder	146.052 mm

[ TABLE 21 ]

(3) Area Table 22 : Natural Ratio vs. Enhanced Natural Ratio

Channel Width	Natural Ratio	Enhanced Natural Ratio
Sail Boat Allocation	104.03 mm	104.03 mm
16 bit Multiplier	444.26 mm	N/A
32 bit Wallace Tree	N/A	130.55 mm
32 bit CLA Adder	N/A	22.38 mm
48 bit Wallace Tree	61.64 mm	124.83 mm
48 bit CLA Adder	154.94 mm	N/A
64 bit CLA Adder	N/A	114.34 mm
32 bit FP Converter	41.77 mm	20.89 mm
96 bit Wallace Tree	30.54 mm	61.08 mm
96 bit CLA Adder	98.96 mm	N/A
128 bit CLA Adder	N/A	146.05 mm
96 bit FP Converter	26.68 mm	26.68 mm
Output Registers	23.40 mm	23.40 mm
Total Channel Width	986.22 mm	774.23 mm

[ TABLE 22 ]