Project 3: Processor Design - Abridged Notes

CS61C Summer 2013

Due Sunday, August 11th, 2013 at 11:59 PM

TA in charge: Justin Fu

Full project specs can be found here.

Project Requirements

Key Differences From MIPS

  1. The zero register isn't special. $r0 is just a regular register like $r1. (This means that add $r1, $r0, $r0 does NOT ALWAYS set $r1 to zero!)
  2. Memory is addressed every 16 bits, or a WORD in our 16-bit architecture. That means each location in memory holds a 16-bit value, unlike MIPS where each location holds 8 bits.
  3. There are only 4 registers, instead of 32.
  4. Data Memory and Instruction Memory are physically separate. Remember that in MIPS, we create the illusion of separate memory with two caches, but we really have only one memory.
  5. Branch delay slots are not exposed to software. You have to deal with them in hardware.
  6. jr is not an R-type instruction. This is because if it was R-type, not all R-types would map directly to an ALU operation. This is purely for your benefit.
  7. The non-variable shifts are also not R-type instructions because there are not enough bits for shamt to exist.

Project Tips

Possible Plan of Attack

These steps are provided just to help you get started if the project spec seems daunting/overwhelming. This is simply a suggested approach, so do what makes the most sense to you. For example, some of you may want to design the control before the datapath.

  1. Take the time to look at some of the Logisim help files: Help --> Library Reference. Knowing how to read these references will help a lot when you start trying to use modules you didn't encounter in homework or lab.
  2. Build the Register File. Test it thoroughly by varying the inputs to make sure it properly reads and stores when enabled.
  3. Design and build your ALU. Again, test it thoroughly using a variety of inputs.
  4. Build your Data Memory circuit following Section 3b of the Deliverables in the project spec and place it in main of cpu.circ. Make sure you understand how to read and write from this memory.
  5. Build a Display Bundle in main of cpu.circ. Make sure you know how it works and that it properly displays (and holds) the values for 16-bit inputs. Then copy this so that you have at least two. Place these somewhere off to the side of main for now.
  6. Import your Register File and ALU into cpu.circ (use Project --> Load Library --> Logisim Library...). Think about any other components you will need for a single-cycle datapath. Build these, and then lay out everything. Wire these components together so that this datapath can execute every instruction our ISA supports. Be sure to identify any control signals you will need to generate.
  7. Design your control (the combinational logic for all of your control signals). The recommended method is the AND logic/OR logic breakdown. Connect the control to the datapath.
  8. Test I- and R-format instructions individually (including loads, stores, and disp).
  9. Convert your single-cycle implementation to a two-cycle datapath.
  10. Test branching and jumping instructions individually and then try whole programs.
  11. Finish writing multsimd.s and octal.s.
  12. Submit your processor and programs.
  13. Rejoice! ... and then sleep.

Back to full project specs.