Project 3: Processor Design

CS61C Summer 2013

Due Sunday, August 11th, 2013 at 11:59 PM

TA in charge: Justin Fu

Based on original spec by Ben Sussman and Brian Zimmer, and modified spec of Albert Chae, Paul Pearce, Noah Johnson, Justin Hsia, Conor Hughes, Anirudh Todi, Ian Vonseggern, and Sung Roa Yoon.
Much thanks to Conor Hughes for an excellent assembler and autograder.

Post any questions or comments to Piazza.

This project spec is ridiculously long, but don't fret! We've spelled out many things in excruciating detail, so if you just take things one-by-one, it won't be as bad as it looks.

We are also providing a set of abridged project notes to look at. These will NOT substitute for reading through the actual project specs, but can be used as a quick reference later on.


Updates | Overview | Deliverables | ISA | Logisim | Testing | Submission

Updates and Clarifications


Updates | Overview | Deliverables | ISA | Logisim | Testing | Submission

Overview

In this project you will be using Logisim to create a 16-bit two-cycle processor. It is similar to MIPS, except that both the datapath and the instructions are 16-bits wide, it has only 4 registers, and memory addresses represent 16-bit words instead of 8-bit bytes (word-addressed instead of byte-addressed).

Please read this document CAREFULLY as there are key differences between the processor we studied in class and the processor you will be designing for this project.

Before you begin, copy the start kit to your home directory (and then possibly to your own machine):

    $ cp -r ~cs61c/proj/su13_proj3 proj03

Pipelining

Your processor will have a 2-stage pipeline:

  1. Instruction Fetch: An instruction is fetched from the instruction memory.
  2. Execute: The instruction is decoded, executed, and committed (written back). This is a combination of the remaining stages of a normal MIPS pipeline.

You should note that data hazards do NOT pose a problem for this design, since all accesses to all sources of data happens only in a single pipeline stage. However, there are still control hazards to deal with. Our ISA does not expose branch delay slots to software. This means that the instruction immediately after a branch or jump is not necessarily executed if the branch is taken. This makes your task a bit more complex. By the time you have figured out that a branch or jump is in the execute stage, you have already accessed the instruction memory and pulled out (possibly) the wrong instruction. You will therefore need to "kill" instructions that are being fetched if the instruction under execution is a jump or a taken branch. Instruction kills for this project MUST be accomplished by MUXing a nop into the instruction stream and sending the nop into the Execute stage instead of using the fetched instruction. Notice that 0x0000 is a nop instruction; please use this, as it will simplify grading and testing. You should only kill if a branch is taken (do not kill otherwise), but do kill on every type of jump.

Because all of the control and execution is handled in the Execute stage, your processor should be more or less indistinguishable from a single-cycle implementation, barring the one-cycle startup latency and the branch/jump delays. However, we will be enforcing the two-pipeline design. If you are unsure about pipelining, it is perfectly fine (maybe even recommended) to first implement a single-cycle processor. This will allow you to first verify that your instruction decoding, control signals, arithmetic operations, and memory accesses are all working properly. From a single-cycle processor you can then split off the Instruction Fetch stage with a few additions and a few logical tweaks. Some things to consider:

You might also notice a bootstrapping problem here: during the first cycle, the instruction register sitting between the pipeline stages won't contain an instruction loaded from memory. How do we deal with this? It happens that Logisim automatically sets registers to zero on reset; the instruction register will then contain a nop. Remember to go to Simulate --> Reset Simulation (Ctrl+R) to reset your processor.


Updates | Overview | Deliverables | ISA | Logisim | Testing | Submission

Deliverables

Approach this project like you would any coding assignment: construct it piece by piece and test each component early and often!

Tidyness and readability will be a large factor in grading your circuit if there are any issues, so please make it as neat as possible! If we can't comprehend your circuit, you will probably receive no partial credit.

1) Register File [show]

2) Arithmetic Logic Unit (ALU) [show]

3) Processor [show]

3a) Data Memory [show]

3b) Output Devices [show]

4) Test Code [show]

*) Extra for Experts: EXTRA CREDIT [show]


Updates | Overview | Deliverables | ISA | Logisim | Testing | Submission

Instruction Set Architecture (ISA)

You will be implementing a simple 16-bit processor with four registers ($r0-$r3). It will have separate data and instruction memory. Because this is a 16-bit architecture, our words are 16 bits wide, unlike the 32-bit MIPS ISA we have been studying in class. For the remainder of this document, a WORD refers to 16 bits. Each of the four registers is big enough to hold ONE word.

IMPORTANT: Because of the limitations of Logisim (and to make things simpler), our memories will be word-addressed (16 bits), unlike MIPS, which is byte-addressed (8 bits).

The instruction encoding is given below. Your processor will pull out a 16-bit value from instruction memory and determine the meaning of that instruction by looking at the opcode (the top four bits, which are bits 15-12). If the instruction is an R-type (i.e. opcode == 0), then you must also look at the funct field.

Notice how we do not use all 64 R-type instructions. Your project only has to work on these specified instructions. This way the project is shorter and easier.

15-12 11 10 9 8 7 6 5 4 3 2 1 0
0 rs rt rd funct See R-type Instructions
1 rs rt offset (signed) bne: branch if not equal
2 rs rt offset (signed) beq: branch if equal
3 target address j: jump to target address
4 rs unused jr:   PC = $rs
5 target address jal into $r3
6 rs rt immediate (signed) addi: $rt = $rs + imm
7 rs rt immediate (unsigned) andi: $rt = $rs & imm
8 rs rt immediate (unsigned) ori:  $rt = $rs | imm
9 rs rt immediate (signed) sw:   MEM[$rs+imm] = $rt
10 rs rt immediate (signed) lw:   $rt = MEM[$rs + imm]
11 rs rt immediate (unsigned) lui:  $rt = imm << 8
12 rs rt immediate (unsigned) disp: DISP[imm] = $rs
13 unused unused immediate (signed) setreg: R[0] = R[1] = R[2] = R[3] = imm
14 rs rt immediate (unsigned) shuff:
$rt[15:8] = imm[1]==1? $rs[15:8] : $rs[7:0]
$rt[7:0] = imm[0]==1? $rs[15:8] : $rs[7:0]

R-Type Instructions
funct Instruction
0 or:   $rd = $rs | $rt
1 and:  $rd = $rs & $rt
2 addp8: $rd = {$rs[15:8] + $rt[15:8] , $rs[7:0] + $rt[7:0] }
3 subp8: $rd = {$rs[15:8] - $rt[15:8] , $rs[7:0] - $rt[7:0] }
4 addh8: $rd = {$rs[15:8] + $rs[7:0] , $rt[15:8] + $rt[7:0] }
5 subh8: $rd = {$rs[15:8] - $rs[7:0] , $rt[15:8] - $rt[7:0] }
6 sllv: $rd = $rs << $rt
7 srlv: $rd = $rs >> $rt (zero extend)
8 srav: $rd = $rs >> $rt (sign extend)
9 add:  $rd = $rs + $rt
10 sub:  $rd = $rs - $rt
11 slt:  $rd = ($rs < $rt) ? 1 : 0

Some specifics on selected instructions:

Shifting

Jumping

Branching

Immediates

Functions not in MIPS Greensheet


Updates | Overview | Deliverables | ISA | Logisim | Testing | Submission

Logisim Notes

Section has been moved to Logisim Notes


Updates | Overview | Deliverables | ISA | Logisim | Testing | Submission

Testing

Once you've implemented your processor, you can test its correctness by writing programs to run on it! First, try this simple program as a sanity check: halt.s. This program loads the same immediate into two different registers using lui/ori and then branches back one instruction (offset = -1) if these registers are equal.

         Assembly:              Binary:
         ========               ======
         lui $r0, 0x33          B033
         ori $r0, $r0, 0x44     8044
         lui $r1, 0x33          B133
         ori $r1, $r1, 0x44     8544
   self: beq $r0, $r1, self     21FF

For practice, verify that the assembly on the left matches the translated binary on the right. This program effectively "halts" the processor by putting it into an infinite loop, so you can observe the outputs as well as memory and register state. Of course, you could do this "halt" with only the beq line, but it is very important that you test your lui/ori or the programs we will use during grading will not work.

To test your processor, open the cpu-harness.circ. Find the Instruction Memory RAM and right click --> Load Image... Select the assembled program (.hex file - see details on the Assembler below) to load it and then start clock ticks.

As described in the Deliverables, you are REQUIRED to write and submit two sample programs to test your processor (octal.s and multsimd.s), but you should also write others to test all your instructions.

Remember: Debugging Sucks. Testing Rocks.

Assembler

We've provided a basic assembler to make writing your programs easier so you can use assembly instead of machine code. You should try writing a few by hand before using this, mainly because it's good practice and makes you feel cooler. This assembler.py supports all of the instructions for your processor.

The assembler is included in the start kit (one you pull from the repo with earlier instruction) or can be downloaded from the link above. The standard assembler is a work in progress, so please report bugs to Piazza!

The assembler takes files of the following form (this is halt.s, which is included in the start kit):

         #Comments are great!
         lui $r0, 0x33          #B033
         ori $r0, $r0, 0x44     #8044
         lui $r1, 0x33          #B133
         ori $r1, $r1, 0x44     #8544
   self: beq $r0, $r1, self     #21FF

Anywhere a register is required, it must be either $r0, $r1, $r2, or $r3. Commas are optional but the '$' is not. '#' starts a comment. The assembler can be invoked with the following command:

   $ python assembler.py input.s [-o output.hex]

The output file is input.hex if not explicitly set - that is, the same name as the input file but with a .hex extension. Use the -o option to change the output file name arbitrarily.


Updates | Overview | Deliverables | ISA | Logisim | Testing | Submission

Submission

You must submit the following files:

   Regfile.circ
   alu.circ
   cpu.circ
   multsimd.s
   octal.s

We will be using our own versions of the *-harness.circ files, so you do not need to submit those. In addition, you should not depend on any changes you make to those files.

You must also submit any .circ files that you use in your solution (they are not copied into your .circ file when you import them, only referenced). Make sure you submit every .circ file that is part of your project! You might want to test your cpu.circ file on the lab machines before you submit it, to make sure you got everything.

Submit in the usual way:

 $ submit proj3 

If you have done the extra credit:

 $ submit proj3-ec 

Grading

This project will be graded in large part by an autograder. Readers will also glance at your circuits. If some of your tests fail the readers will look to see if there is a simple wiring problem. If they can find one they will give you the new score from the autograder minus a deduction based on the severity of the wiring problem. For this reason and as neatness is a small part of your grade please try to make your circuits neat and readable.


Updates | Overview | Deliverables | ISA | Logisim | Testing | Submission