Due Wednesday, July 11, 2012 @ 11:59pm
Goals
This assignment will cover floating points and caches.
Submission
Put all your answers in hw3.txt
.
Submit your solution by creating a directory named hw3
that contains the file hw3.txt
.
(File names are case-sensitive and the submission program will not
accept your submission if your file names differ at all from those
specified) From within that directory, type submit hw3
. Partners are not allowed on this assignment.
Copy the contents of ~cs61c/hw/03
to a suitable location in your home directory to obtain files you will want for this homework.
$ cp -r ~cs61c/hw/03/ ~/hw3
Exercises
Problem 1: Floating Points - 4pts
For the following questions, we will be referring to the IEEE 32-bit floating point representation except with a 4 bit exponent (bias of 2^4/2 - 1 = 7) and a denorm implicit exponent of -6.- Convert the following -62.25. Write your answer in hexadecimal.
- What's the smallest positive integer (an integer has no decimal points) it CANNOT represent? Leave your answer in decimal.
- What's the smallest positive value it can represent that is not a denorm? Does the implicit exponent make sense?
- What's the smallest positive value it can represent? Leave your answer as the closest power of 2.
Problem 2: Performance - 1pt
You came up with an instruction set SUPER that contains a bunch of very cool instructions that MIPS would require many instructions to do. With SUPER, you would be able to write program X into half as many instructions as if you were to compile it into MIPS. You decide to build a SUPER machine. However, because of the complexity of some instructions, you have to halve the clock rate. Moreover, you found that the average number of cycles per instruction of a SUPER machine you built is 50% more than a MIPS machine. Based on just the given information, which machine do you expect to take more CPU time on program X? By how much longer do you expect?
Problem 3: Caches - 5pts
Assume we have 8 bit byte-addresses. A very tiny cache holds a total of 16 bytes and each cache block is a word wide.
- If the cache is direct-mapped...
- How many bits are used for the tag?
- Which other bytes would share a block with the byte at address 0x83?
- The block containing the byte at 0x83 is in the cache. What memory accesses are guaranteed to get a cache miss? You may describe what addresses, but be specific.
- If the cache is two-way set associative...
- How many bits are used for the tag?
- Which other bytes would share a block with the byte at address 0x83?
- The block containing the byte at 0x83 is in the cache. What memory accesses are guaranteed to get a cache miss? You may describe what addresses, but be specific.
- The hit time is a clock cycle, and the miss penalty is 50. If the miss rate is 50%, what is the AMAT?