In this lab, you're going to get a head start on Project 3-1 and a little practice thinking about pipelining. Please go to the Project 3-1 spec for instructions on how to get the files for Project 3-1.
For the lab files, pull them as usual from your lab directory using the following command:
$ git pull starter master
To get you started thinking about the register file and ALU, we have a short introductory edX assignment. You can find it linked here.
- Show the TA or AI checking you off that you completed the edX assignment and got 100%. Only one partner has to finish the assignment; you should work on it together.
RegFile and ALU
Time for the fun part! Get started working on your Register File and ALU. To get full credit, you must either pass 2/4 RegFile tests and 2/8 ALU tests or pass 6/8 of the ALU tests. (Even better, pass all 12 tests!)
- Show the TA or AI checking you off the result of running test.sh.
Project 3-2 will involve producing a fully functional, 2-stage pipelined CPU in Logisim. Pipelining can be a tricky concept to grasp, so we're going to do a short exercise to get you started thinking about it.
Assume that on power-on, registers initially contain zeros.
Consider the following 2-input FSM. Its next state and output is computed by multiplying the inputs and adding it to the current state.
Say the propogation delay of a adder block is 50ns, the propogation delay of a multiplication block is 55 ns, and the clk-to-q delay of a register is 5ns. Calculate the maximum clock rate at which this circuit can operate. Assume that the register setup time is negligible, and that both inputs come from clocked registers that receive their data from an outside source.
- Show your TA the calculations you performed to find the maximum clock rate (non-pipelined).
We want to improve the performance of this circuit, and let it operate at a higher clock rate. To do so, we will divide up the multiplication and addition into two different pipeline stages; in the first pipeline stage, we will perform the multiplication of the two inputs. In the second pipeline stage, we will add the product to the state.
Our definition of "correctness" will be simple: we will consider the sequence of outputs from this circuit "correct" iff it corresponds to the sequence of outputs the non-pipelined version would emit, potentially with some leading zeros. For example, if for some sequence of inputs the non-pipelined version emits [3,5,1,2,4, ...], a correct circuit might emit the sequence of outputs [0,3,5,1,2,4, ...] for that same sequence of inputs.
For your convenience and to help standardize check-offs, we are providing a starting point in the files pipeline.circ and ROMData. In pipeline.circ, the sub-circuit Non-pipelined is set up exactly as the figure above. The main circuit is set up to produce the output sequence [3,5,1,2,4,-1,0,0,...] on the non-pipelined version of this circuit. It is also a handy example of how to use memory from a file. The ROM block should be initialized to the proper data, but if it is zero-ed out, right-click it and choose "Load image..." and select ROMdata.
Note that we need a register to hold the intermediate value of the computation between pipeline stages. This is a general theme with pipelines.
- Complete the sub-circuit Pipelined. You will need to add a register to divide the multiplication and addition into separate pipeline stages.
- Calculate the maximum clock rate for the pipelined version of the circuit.
- Show your TA the completed, pipelined circuit.
- Show your TA the calculations you performed to find the maximum clock rate (pipelined).
- The TA or AI checking you off will ask you one of the clicker questions from Monday October 29 (Single Cycle Datapath I), Wednesday October 31 (Single Cycle Datapath II), or Friday November 2 (Single Cycle Control).