CS61C Fall 2016 Project 3-1: ALU and Regfile

TA: Rebecca Herman

Due Friday, 10/21, 2016 @ 11:59 PM

Updates and Clarifications


In this project you will be using Logisim to implement a simple 32-bit two-cycle processor. Throughout the implementation of this project, we'll be making design choices that make it compatible with machine code outputs from MARS and your Project 2! When you're done, you'll be able to run most, but not all, instances of MIPS code through your assembler and linker, and then on your very own CPU! We have left out some functionality to make the project easier.

In part I, you will make the Regfile and ALU.


0) Obtaining the Files

Similarly to project 2, we will be distributing the project files through Bitbucket, and you may have a partner. You can look back on the step 0 for project 2 for more specific steps. However, make sure that you are using your newly created project 3 repository! The repository that contains the starter code is named proj3-starter.

An abridged version of the commands is reproduced below:

cd ~                            # Make sure you are outside of any existing repositories (eg. ~/work)
git clone https://bitbucket.org/mybitbucketusername/proj3-xxx.git # or proj3-xxx-yyy.git if you're working with a partner
cd proj3-xxx
git remote add proj3-starter https://github.com/61c-teach/fa16-proj3-starter.git
git fetch proj3-starter
git merge proj3-starter/proj3-1-starter

1) Register File

Your task is to implement all 32 registers promised by the MIPS ISA (use the built-in Logisim registers!). Your regfile should be able to write to or read from any register specified in a given MIPS instruction without affecting any other registers. There is one notable exception: your regfile should NOT write to $0, even if an instruction should try. Remember that the Zero Register should ALWAYS have the value 0x0. You should NOT gate the clock at any point in your regfile: the clock signal should ALWAYS connect directly to the clock input of the registers without passing through ANY combinational logic.

You are provided with the skeleton of a register file in regfile.circ. The register file circuit has six inputs:

Input Name Bit Width Description
Clock 1 Input providing the clock. This signal can be sent into subcircuits or attached directly to the clock inputs of memory units in Logisim, but should not otherwise be gated (i.e., do not invert it, do not "and" it with anything, etc.).
Write Enable 1 Determines whether data is written on the next rising edge of the clock.
Read Register 1 5 Determines which register's value is sent to the Read Data 1 output, see below.
Read Register 2 5 Determines which register's value is sent to the Read Data 2 output, see below.
Write Register 5 Determines which register to set to the value of Write Data on the next rising edge of the clock, assuming that Write Enable is a 1.
Write Data 32 Determines what data to write to the register identified by the Write Register input on the next rising edge of the clock, assuming that Write Enable is 1.

The register file also has the following six outputs:

Output Name Bit Width Description
Read Data 1 32 Driven with the value of the register identified by the Read Register 1 input.
Read Data 2 32 Driven with the value of the register identified by the Read Register 2 input.
$s0 Value 32 Always driven with the value of $s0 (This is a DEBUG/TEST output.)
$s1 Value 32 Always driven with the value of $s1 (This is a DEBUG/TEST output.)
$s2 Value 32 Always driven with the value of $s2 (This is a DEBUG/TEST output.)
$ra Value 32 Always driven with the value of $ra (This is a DEBUG/TEST output.)
$sp Value 32 Always driven with the value of $sp (This is a DEBUG/TEST output.)

The outputs $s0-$s2, $ra, and $sp are present because those registers are more special than the others - they are for testing and debugging purposes, and will be used in the autograder tests! If you were implementing a real regfile, you would omit those outputs. In our case, be sure they are included correctly! If they are not, we won't be able to grade your submission (and you'll get a zero. :( ).

You can make any modifications to regfile.circ you want, but the outputs must obey the behavior specified above. In addition, your regfile.circ that you submit must fit into the regfile-harness.circ file we have provided for you. This means that you should take care to not reorder inputs or outputs. If you need more space, however, you can move them around if you are careful and maintain their relative positioning to each other. To verify your changes didn't break anything, simply open regfile-harness.circ and ensure there are no errors and the circuit functions well. We will be using a similar file to test your register file for grading, so you should download a fresh copy of regfile-harness.circ and make sure your regfile.circ is cleanly loaded before submitting.

HINTS: Muxes and demuxes are your friends. I would advise you not to use the enable input on your Muxes. In fact, you can turn that feature off. I would would advise you to also turn "three-state?" to off. Take a look at all the inputs to a logisim register and see what they do.

2) Arithmetic Logic Unit (ALU)

Your second task is to create an ALU that supports all the operations needed by the instructions in our ISA (which is described in further detail in the next section). The ISA mostly consists of instructions from the MIPS ISA, though there may be additional "new" instructions... Fortunately, you don't have to try to figure out all the required operations as we provide the list to you.

We have provided a skeleton of an ALU for you in alu.circ. It has three inputs:

Input Name Bit Width Description
X 32 Data to use for X in the ALU operation.
Y 32 Data to use for Y in the ALU operation.
Switch 4 Selects what operation the ALU should perform
(see the list of operations with corresponding switch values below).

... and four outputs:

Output Name Bit Width Description
Signed Overflow 1 High iff the operation was an add or sub and there was signed overflow; low otherwise.
Equal 1 High iff the two inputs X and Y are equal; low otherwise.
Result 32 Result of the ALU Operation.
Result2 32 Contains the upper 32 bits of mult when the function is mult, or the remainder of divu when the instruction is divu. Contains some unspecified 32-bit value on other instructions.

And as previously promised, here is the list of operations that you need to implement (along with their associated Switch values). You are allowed and encouraged to use built-in logisim blocks to implement the arithmetic operations.

Switch Value Instruction
0 sll: Result = Y << X
1 srl: Result = Y >>> X
2 sra: Result = Y >> X
3 mult: Result = X*Y[31:0]; Result2 = X*Y[63:32]
4 divu: Result = X/Y; Result2 = X%Y (unisgned)
5 add: Result = X + Y (Set Signed Overflow if overflow)
6 addu: Result = X + Y
7 sub: Result = X - Y (Set Signed Overflow if overflow)
8 subu: Result = X - Y
9 and: Result = X & Y
10 or: Result = X | Y
11 xor: Result = X^Y
12 nor: Result = ~(X|Y)
13 slt: Result = (X < Y) ? 1 : 0 Signed
14 sltu: Result = (X < Y) ? 1 : 0 Unsigned

If Result2 is not specified, its behavior is undefined, and it can have any value. It should still have some defined value (X's are never OK!) but it doesn't matter what that value is, or if that value is constant or varying.

NOTE: It looks strange that we ask you to implement signed multiplication and unsigned division... The multiplier circuit built into logisim is signed (when operating on 32-bit numbers), and the division block is unsigned! You are NOT expected to implement multiply or divide from scratch.

Tl;dr: Use the built-in multiply and divide blocks, and don't worry about it.

Some additional things to keep in mind:

Note: Your ALU must be able to fit in the provided harness alu_harness.circ. Follow the same instructions as the register file regarding rearranging inputs and outputs of the ALU. In particular, you should ensure that your ALU is correctly loaded by a fresh copy of alu-harness.circ before you submit.

Logisim Notes

If you are having trouble with Logisim, RESTART IT and RELOAD your circuit! Don't waste your time chasing a bug that is not your fault. However, if restarting doesn't solve the problem, it is more likely that the bug is a flaw in your project. Please post to Piazza about any crazy bugs that you find and we will investigate.

Things to Look Out For

Logisim's Combinational Analysis Feature

Logisim offers some functionality for automating circuit implementation given a truth table, or vice versa. Though not disallowed (enforcing such a requirement is impractical), use of this feature is discouraged. Remember that you will not be allowed to have a laptop running Logisim on the final.


For part 1, we have provided you with a script for running tests on the ALU and regfile called "run-sanity-test.sh". Running ./run-sanity-test.sh will copy your alu and regfile into the tests directory and run two ALU tests and two Regfile tests, which are stored in the tests directory as well. These tests drop in your work into a very slightly modified version of the harness and run it with a small set of inputs. The output is then compared against the provided reference.

If you fail a test and want to figure out what went wrong, you can go into your tests folder and open the harness corresponding to that test. Right click on your regfile or ALU and choose "view main." You can then see your refile with the inputs provided by the test. Make sure your regfile or ALU behaves the way it ought to!

Keep in mind, as always, that the tests we provided are not comprehensive. But fortunately, we also provided you with a script to help you create tests, called "make_alu_test.py". Take a look at the file called TESTING INSTRUCTIONS to see how you can make your own tests. Basically, you'll want to come up with the values to put inside the different memory units to exercise different behaviors of the ALU and RegFile. If you run python make_alu_test.py, the script will create most of the necessary files for you in the propper format, and will tell you what to do.

Note: the autograder only works with python 2.7, so it may be easier to run it remotely off of the hive* servers if you haven't set up your python environments.


There are two steps required to submit proj3-1. Failure to perform both steps will result in loss of credit:

  1. First, you must submit using the standard unix submit program on the instructional servers. This assumes that you followed the earlier instructions and did all of your work inside of your git repository. To submit, follow these instructions after logging into your -XX class account:

    cd ~/proj3-XXX                             # Or where your shared git repo is
    submit proj3-1

    Once you type submit proj3-1, follow the prompts generated by the submission system. It will tell you when your submission has been successful and you can confirm this by looking at the output of glookup -t.

  2. Additionally, you must submit proj3-1 to your shared Bitbucket repository:

    cd ~/proj3-XXX                             # Or where your shared git repo is
    git add -u                           
    git commit -m "project 3-1 submission"  
    git tag "proj3-1-sub"                        # The tag MUST be "proj3-1-sub". Failure to do so will result in loss of credit.
    git push origin proj3-1-sub                  # This tells git to push the commit tagged proj3-1-sub


If you need to re-submit, you can follow the same set of steps that you would if you were submitting for the first time, but you will need to use the -f flag to tag and push to Bitbucket:

# Do everything as above until you get to tagging
git tag -f "proj3-1-sub"
git push -f origin proj3-1-sub

Note that in general, force pushes should be used with caution. They will overwrite your remote repository with information from your local copy. As long as you have not damaged your local copy in any way, this will be fine.



We will be using our own versions of the *-harness.circ files, so you do not need to submit those. In addition, you should not depend on any changes you make to those files.


This project will be graded in large part by an autograder. If you would like a regrade, we will give you a chance to request one, but we will also automatically deduct 5% from your final proj3-1 grade, unless it is an error with our test cases.