Due Wednesday, November 4th, 2015 @ 11:59 PM
Updates and Clarifications
- 11/05/2015 @3:47 PM: Tests are released and operational
- 11/04/2015: Extended Project Deadline to November 6th @11:59
- 10/30/2015 @ 12:30 AM: Extended Project Deadline to November 4th @11:59
- 10/26/2015 @ 3:30 PM: Updated Obtaining the Files section with fixed instructions if proj3-1 remote was not present.
- 10/26/2015 @ 3:30 PM: Correct the format type specification for swinc - originally said it was R-type but should be I-type.
IMPORTANT INFO - PLEASE READ
- You are allowed to use any of Logisim's built-in blocks for all parts of this project.
- Save often. Logism can be buggy and the last thing you want is to lose some of your hard work. There are students every semester who have had to start over large chunks of their projects due to this.
- Approach this project like you would any coding assignment: construct it piece by piece and test each component early and often!
- Sample tests for a completed ALU and Regfile have been included in the proj3-1StartKit - just run the bash script run-sanity-test.sh. We recommend running the sample tests locally, but they only work with python 2.7. As always, keep in mind that these tests are NOT comprehensive and you will need to do further testing on your own.
- Tidyness and readability will be a large factor in grading your circuit if there are any issues, so please make it as neat as possible! If we can't comprehend your circuit, you will probably receive no partial credit.
- MAKE SURE TO CHECK YOUR CIRCUITS WITH THE GIVEN HARNESSES TO SEE IF THEY FIT! YOU WILL FAIL ALL OUR TESTS IF THEY DO NOT.
(This also means that you should not be moving around given inputs and outputs in the circuits). - Because the files you are working on are not plain code and circuit schematics, they can't really be merged. DO NOT WORK ON THE SAME FILE IN TWO PLACES AND TRY TO MERGE THEM. YOU WILL NOT BE ABLE TO MERGE THEM AND YOU WILL BE SAD. Collaborate with your partner in person or work on the ALU and RegFile separately. Never work on the same thing together while on separate computers.
Overview
In this project you will be using Logisim to implement a simple 32-bit two-cycle processor. Throughout the implementation of this project, we'll be making design choices that make it compatible with machine code outputs from MARS and your Project 2! When you're done, you'll be able to run MIPS code through your assembler and linker, and then on your very own CPU :D
In part II, you will complete a 2-stage pipelined processor!
0) Obtaining the Files
We have added the CPU template (cpu.circ) and harness (run.circ), the data memory module (mem.circ), and a basic assembler (assembler.py) to help you test your CPU. Please fetch and merge the changes from the proj3-2 branch of the starter repo. For example, if you have set the proj3-starter remote link:
cd proj3-XX-YY # Go inside the project directory git fetch proj3-starter git merge proj3-starter/proj3-2 -m "merge proj3-2 skeleton code"
If you do not have the proj3-starter remote link from part I, you can run:
git remote add proj3-starter https://github.com/cs61c-fall2015/proj3-starter.git
If you do have some other inorrect value for the proj3-starter remote link, delete it first by running:
git remote rm proj3-starter
1) Getting Started - Processor
We have provided a skeleton for your processor in cpu.circ. Your processor will contain an instance of your ALU and Register File, as well as a memory unit provided in your starter kit. You are also responsible for implementing Hi and Lo and constructing the entire datapath and control from scratch. Your completed processor should implement the ISA detailed below in the section Instruction Set Architecture (ISA) using a two-cycle pipeline, specified below.
Your processor will get its program from the processor harness run.circ. Your processor will output the address of an instruction, and accept the instruction at that address as an input. Inspect run.circ to see exactly what's going on. (This same harness will be used to test your final submission, so make sure your CPU fits in the harness before submitting your work!) Your processor has 2 inputs that come from the harness:
Input Name | Bit Width | Description |
INSTRUCTION | 32 | Driven with the instruction at the instruction memory address identified by the FETCH_ADDRESS (see below). |
CLOCK | 1 | The input for the clock. As with the register file, this can be sent into subcircuits (e.g. the CLK input for your register file) or attached directly to the clock inputs of memory units in Logisim, but should not otherwise be gated (i.e., do not invert it, do not AND it with anything, etc.). |
Your processor must provide 7 outputs to the harness:
Output Name | Bit Width | Description |
$s0 | 32 | Driven with the contents of $s0. FOR TESTING |
$s1 | 32 | Driven with the contents of $s1. FOR TESTING |
$s2 | 32 | Driven with the contents of $s2. FOR TESTING |
$ra | 32 | Driven with the contents of $ra. FOR TESTING |
Hi | 32 | Driven with the contents of Hi. FOR TESTING |
Lo | 32 | Driven with the contents of Lo. FOR TESTING |
FETCH_ADDRESS | 32 | This output is used to select which instruction is presented to the processor on the INSTRUCTION input. |
ONE MORE THING: In addition to these inputs and outputs, you also need to have an LED unit which lights up to signify signed overflow. This indicator should be wired to the signed overflow port of your ALU. This should be viewable in your main circuit.
Just like in part I, be careful not to move the input or output pins! You should ensure that your processor is correctly loaded by a fresh copy of run.circ before you submit. You can download a fresh copy from the starter repo website.
1.5) Getting Started - Memory
The memory unit is already fully implemented for you! Here's a quick summary of its inputs and outputs:
Output Name | In- or Out-put? | Bit Width | Description |
A: ADDR | In | 32 | Address to read/write to in Memory |
D: WRITE DATA | In | 32 | Value to be written to Memory |
En: WRITE ENABLE | In | 1 | Equal to one on any instructions that write to memory, and zero otherwise |
Clock | In | 1 | Driven by the clock input to cpu.circ |
Unit: OP UNIT | In | 3 | Differentiates between word, half and byte operations, as well as signed vs. unsigned. More detail in a table directly following |
D: READ DATA | Out | 32 | Driven by the data stored at the specified address. For bytes and halves, the data is right-justified, and the value is extended as specified in OP UNIT. |