There are two parts to this lab. In the first part, you will be learning how to use the remaining essential parts of logisim, in particular, splitters to take a subset of bits on a wire, and to rejoin them. In the second part, you will gain some hands-on experience with pipelining.
P&H 4.5, 4.6 (4th edition)
Refer to the Logisim Website or last week's lab for a refresher on Logisim.
The following exercises will introduce you to how wires work in logism.
Show your Exer1 circuit. | |
Tell your TA a more meaningful name for the Exer1 circuit. |
rotr
, which stands for "Rotate Right". The idea is that rotr A,B
will "rotate" the bit pattern of input A to the right by B bits. So, if A were 1011010101110011 and B were 0101 (5 in decimal), the output of the block would be 1001110110101011. Notice that the rightmost 5 bits were rotated off the right end of the value and back onto the left end. In RTL, the operation would be something like "R = A >> B | A << (16 - B)
".
You must implement a subcircuit named "rotr" with the following inputs:
rotr
subcircuit in the main subcircuit.
Hint: Before you start wiring, you should think veeeerrrry carefully about how you might decompose this problem into smaller ones and join them together. You should feel very free to use subcircuits when implementing rotr
. If you don't, expect to regret it.
Show your TA your rotr circuit and verify that it works |
This next exercise will get you some hands-on practice with pipelining. Assume that on power-on, registers initially contain zeros.
Consider the following 2-input FSM. Its next state and output is computed by multiplying the inputs and adding it to the current state.
Say the propogation delay of a adder block is 50ns, the propogation delay of a multiplication block is 50 ns, and the clk-to-q delay of a register is 5ns. Calculate the maximum clock rate at which this circuit can operate. Assume that the register setup time is negligible, and that both inputs are clocked registers that receive their data from an outside source.
Show your TA the calculations you performed to find the maximum clock rate. |
We want to improve the performance of this circuit, and let it operate at a higher clock rate. To do so, we will divide up the multiplication and addition into two different pipeline stages; in the first pipeline stage, we will perform the multiplication of the two inputs. In the second pipeline stage, we will add the product to the state.
Our definition of "correctness" will be simple: we will consider the sequence of outputs from this circuit "correct" iff it corresponds to the sequence of outputs the non-pipelined version would emit, potentially with some leading zeros. For example, if for some sequence of inputs the non-pipelined version emits [3,5,1,2,4, ...], a correct circuit might emit the sequence of outputs [0,3,5,1,2,4, ...] for that same sequence of inputs.
Note that we need a register to hold the intermediate value of the computation between pipeline stages. This is a general theme with pipelines.
Show your TA the completed, pipelined circuit. | |
Show your TA the calculations you performed to find the maximum clock rate. | |
Explain to your TA why bubbles are unecessary in this circuit. |