Wk |
Date |
Lecture Topic |
Reading |
Section |
Lab |
Assignment Due
|
1
|
08.27 F |
Introduction and C vs. Assembly--
Introduction (2 up),
(6 up) |
|
|
|
|
2
|
08.30 M |
HW/SW Interface: C vs. Assembly--
Operands (2 up),
(6 up) |
P&H (4th): 2.1-2.3, 2.6 |
Section 1:
Read K&R
Ch 2, Ch 3,
Ch 6: 6.1, 6.2 |
Lab 1, Part 1: C Environment and Strings |
HW#1: HW/SW interface
Solution |
09.01 W |
HW/SW Interface: C vs. Assembly--
Characters (2 up),
(6 up) |
P&H (4th): 2.9, 2.7 |
09.03 F |
HW/SW Interface: C vs. Assembly--
Functions (2 up),
(6 up) |
P&H (4th): 2.14, 2.8 |
3
|
09.06 M |
Holiday |
Section 2:
Read K&R
Ch 4, Ch 5 |
Lab 1, Part 2: More C: Pointers and Number Representation |
HW#2: rgrep Due Friday@23:59:59 rubric |
09.08 W |
HW/SW Interface: C vs. Assembly--
Numbers (2 up),
(6 up) |
P&H (4th): 2.4, 3.5 (pp. 242-250 |
09.10 F |
HW/SW Interface: C vs. Assembly--
Instructions (2 up),
(6 up) |
P&H (4th): 2.4, 2.5, 2.9, 2.10,
2.12 (pp. 139-142), 2.13, 3.5 (pp. 242-250, 259-266), 3.8 |
4
|
09.13 M |
Floating Point and Pointers Revisited
(2 up),
(6 up) |
P&H (4th): 2.14, 3.5, 3.8 |
Section 3 |
Lab 2, Part 1: Assembly Practice |
Project#1: MIPS Instruction Set Emulator
Two Weeks, Due Saturday 9/18 (Part 1), 9/25 (Part 2)@23:59:59
Rubric |
09.15 W |
Technology Trends and
Components of a Computer
(2 up),
(6 up) |
P&H (4th): 1.1-1.3 |
09.17 F |
Datacenters and Cloud Computing
(2 up),
(6 up) |
Warehouse-Scale Computers
(PDF): Ch 1, Ch 3, Ch 5.1-5.3 |
5
|
09.20 M |
Request and Data-Level Parallelism
(2 up),
(6 up) |
WSC: 2.4 |
Section 4 |
Lab 2, Part 2: More Assembly Practice |
09.22 W |
Compilation vs. Interpretation
(2 up),
(6 up) |
P&H (4th): 2.12, B.1-B.4 |
09.24 F |
Quantitative Evaluation
(2 up),
(6 up) |
|
6
|
09.27 M |
Quantitative Evaluation
(2 up),
(6 up)
|
|
Section 5 |
Lab 3, Part 1: Cache Blocking |
HW#3: C/MIPS and Caches Solution |
09.29 W |
Memory Hierarchy:
Direct Mapped Caches
(2 up),
(6 up) |
P&H (4th): 5.1 |
10.01 F |
Memory Hierarchy:
Cache-Memory Interface
(2 up),
(6 up) |
P&H (4th): 5.2 (pg. 457-470) |
7
|
10.04 M |
Memory Hierarchy:
Cache Performance
(2 up),
(6 up) |
P&H (4th): 5.3 (pg. 474-479) |
Section 6 |
Lab 3b: EC2 |
|
10.06 W |
Midterm (6-9 PM),
Pimental 1
solutions/rubric |
|
10.08 F |
Data Level Parallelism:
Flynn Taxonomy
(2 up),
(6 up) |
P&H (4th): 1.5, 1.6, 7.1, 7.2 |
|
8
|
10.11 M |
Data Level Parallelism:
Intel SSE SIMD Instructions
(2 up),
(6 up) |
P&H (4th): 7.4, 7.7 |
Section 7 |
Lab 4, Part 1: Data Parallelism |
Project 2: PageRank (MapReduce)
Two Weeks:
Part One, Due Saturday 10/16@23:59:59
Part Two, Due Saturday, 10/23@23:59:59 |
10.13 W |
Thread Level Parallelism
(4 up)
(6 up)
(.pptx)
|
P&H (4th): 7.3, 5.8 |
10.15 F |
Thread Level Parallelism
(4 up)
(6 up)
(.pptx)
|
P&H (4th): 2.11 |
9
|
10.18 M |
Thread Level Parallelism
(4 up)
(6 up)
(.pptx)
|
|
Section 8 |
Lab 4, Part 2: Thread Parallelism |
10.20 W |
Transistors to Gates
(2 up),
(6 up) |
P&H (4th): C.2-C.3 (on CD),
Logic Handout |
10.22 F |
State and State Machines
(2 up),
(6 up) |
P&H (4th): 4.2, C.3-C.6 (on CD),
State Handout
|
10
|
10.25 M |
Multiplexers and ALUs
(2 up),
(6 up) |
Blocks Handout;
SDS Handout |
Section 9 |
Lab 5: Logisim |
HW 4: Digital Design and FSMs Solution |
Due Friday@23:59:59
10.27 W |
Single Cycle CPU Datapath
(2 up),
(6 up) |
|
10.29 F |
Single Cycle CPU Datapath (cont.)
(2 up),
(6 up) |
|
11
|
11.01 M |
Single Cycle CPU Control
(2 up),
(6 up) |
P&H (4th): 4.1, 4.3, 4.4 |
Section 10 |
Lab 5, part 2: More logisim! |
Project 3: Performance Improvement
Two Weeks, Due Saturday, 11/13@23:59:59 |
11.03 W |
Instruction Level Parallelism
(4 up),
(6 up),
(.pptx) |
P&H (4th): 4..1, 4.3, 4.4 |
11.05 F |
Instruction Level Parallelism
(4 up),
(6 up),
(.pptx)
|
P&H (4th): 4.5-4.6 |
12
|
11.08 M |
Instruction Level Parallelism
(4 up),
(6 up),
(.pptx)
| P&H (4th): 4.7-4.8 |
Section 11 |
Optional logisim lab (no official lab due to Veterans' day) |
11.10 W |
Set-Associative Caches
(2 up),
(6 up) |
P&H (4th): Rest of 5.2, 5.3 |
11.12 F |
Multi-Level Caches
(2 up),
(6 up) |
P&H (4th): 5.8 |
13
|
11.15 M |
C Malloc and Free
(2 up),
(6 up) |
P&H (4th): 5.3-5.5, 5.10-5.12 |
Section 12 |
Lab 6: Free Store and Debugging |
Project 4: Processor Design
Two Weeks, Due Saturday, 11/27@23:59:59
|
11.17 W |
Virtual Memory
(4 up),
(6 up),
(.pptx)
|
P&H (4th): 5.3-5.5, 5.10-5.12
P&H (4th): C.8 |
11.19 F |
Virtual Memory
(4 up),
(6 up),
(.pptx)
|
P&H (4th): 6.2,
P&H (4th): C.8 (pg. C-65 to C-67) |
14
|
11.22 M |
Traps, Virtual Machines
(4 up),
(6 up),
(.pptx)
|
|
Section 13 |
|
11.24 W |
Economics of Cloud Computing
(2 up),
(6 up) |
Warehouse-Scale Computers
(PDF): Ch 1, Ch 3, Ch 5.1-5.3 |
11.26 F |
Thanksgivings Holiday |
15
|
11.29 M |
Anatomy of a Modern Microprocessor
A Personal History of RISC
(4 up),
(6 up),
(.pptx),
1981 RISC talk slides
|
|
Section 14 |
EC Due Date 11/29@23:59:59 |
Face to Face Project 4 Grading (during lab time) |
12.01 W |
Programming Contest Results
A Personal History of RAID
(2 up),
(6 up) |
Berkeley RAID Paper (PDF) |
|
12.03 F |
Cal Cultural Heritage
(4 up),
(6 up),
(.pptx)
Course Wrap-up
(2 up),
(6 up) |
|
|
Reading Week
|
12.06 M |
Final Exam Review, 2-5 PM, 10 Evans Questions (solutions) |
Finals
|
12.13 M |
Final Examination, 8-11 AM, 220 Hearst Gym |