Two questions, submit as "quiz36". Due 2:45pm before lecture 11/28/2007.
For this quiz consider the following I/O system characteristics:
A 800MHz I/O system.
A memory system support block reads of 4 to 32 32bit words.
A 64bit connection between the memory and CPU, with each 64bit transfer taking 1 clock cycle.
1 cycle of latency when transmitting an address from the CPU to the memory. In other words it takes on clock cycle to transmit the address to the memory.
2 clock cycles of idle between each bus transaction. That is each pair of reads or writes must be separated by 2 idle clock cycles, in which neither address nor data may be transmitted.
A memory read latency of 200ns for the first 4 32bit words, and an additional 2.5ns for each subsequent block of 4 words.
Assume that the transfer of the first four words of data can overlapped with the read of the next four words, and so on.
To answer these questions you may wish to create a timing diagram (wave window style) or something similar to your old pipelining diagrams.
Consider making an ordered list of the actions which are part of a memory access, and then assigning a duration to each of them, to find the total time.
Be sure to take into account which actions may be overlapped in time.
1.
Find the sustained read bandwidth (number of bytes per second) using 4word block accesses.
2.
Find the total latency (number of clock cycles) of a 256word read using 32word block accesses.