CS 61C (Fall 2007)

Quiz 34

Two questions, submit as "quiz34". Due 2:45pm before lecture 11/21/2007.

1.

Consider a virtual memory system with the following properties:

38-bit virtual byte address
16KB pages
32-bit physical byte address
There are valid, protected, dirty and use bits for each page
Disk addresses are not stored in the page table
Page table entries are byte-aligned

How many pages does the page table for each process require?

2.

Below are the eight combinations of TLB, Page Table and Cache hit or miss. Please list all of the possible situations by their row number. You may to wish explain very briefly.

Row Number	TLB	Page Table	Cache
0	hit	hit	hit
1	hit	hit	miss
2	hit	miss	hit
3	hit	miss	miss
4	miss	hit	hit
5	miss	hit	miss
6	miss	miss	hit
7	miss	miss	miss