CS 61C (Fall 2007)

Quiz 32

One question, submit as "quiz32".  Due 2:45pm before lecture 11/16/2007.


1.

Consider three processors with different cache configurations and miss rate measurements.

CacheCache DesignMeasured Miss Rate
ConfigurationBlock SizeInstructionData
1Direct-Mapped1-word4%6%
2Direct-Mapped4-words2%4%
32-way set associative4-words2%3%
Which cache will end up spending the largest number clock cycles on cache misses? Show your work.