CS 61C (Fall 2007)

Quiz 29

Two questions, submit as "quiz29". Due 2:45pm before lecture 11/7/2007.

Consider executing the following MIPS assembly language fragments on the pipelined datapath of Figure 6.36 on page 416 of P&H:

1.

addu $2, $3, $1
subu $4, $3, $5
addu $5, $3, $7
addu $7, $6, $1
addu $8, $2, $6

At the end of the fifth clock cycle of execution (the first instruction is being fetched on the first cycle), which registers are being read and which register will be written? Please explain very briefly.

Please be sure to format your answer according to template.txt.

2.

lw $4, 100($2)
subu $5, $4, $3
subu $2, $3, $5

How many clock cycles will it take to execute this code, including fetching the load, and completing both subtractions? Please explain very briefly.

You may find it helpful to draw diagrams similar to Figure 6.34 and 6.35, illustrating what the dependencies are, and how the code will actually be executed (incorporating and stalls or forwarding).