CS 61C (Fall 2007) |
Quiz 25Two question, submit as "quiz25". Due 2:45pm before lecture 10/26/2007. |
MemToReg
be set to during a lw
instruction? Format you answer as a Verilog constant.
Please explain very briefly.Branch
and
ALUOp0
are identical, and thus we might get rid of one (either one, it doesn't matter). Are there
any other control signals we could do without by reusing an existing signal? This may require the use of an inverter to
invert the control signal, or it may exploit don't cares.