CS61C: Machine Structures. Fall 2007, UC Berkeley
Patterson and Hennessey Kernighan and Ritchie
CS61C Fall 2007
MWF 3pm-4pm 2050 VLSB





CS 61C (Fall 2007)

Quiz 25

Two question, submit as "quiz25".  Due 2:45pm before lecture 10/26/2007.


1.

Refering to the datapath & processor design presented in P&H 5.3, what should MemToReg be set to during a lw instruction? Format you answer as a Verilog constant.  Please explain very briefly.

2.

This question refers to the lower half of Figure 5.22 on page 312 of P&H.

The control signals Branch and ALUOp0 are identical, and thus we might get rid of one (either one, it doesn't matter). Are there any other control signals we could do without by reusing an existing signal?  This may require the use of an inverter to invert the control signal, or it may exploit don't cares.

If you can find a signal which may be optimized away, tell us the name of the signal which could be replaced.  If two are identical, you may give either as the answer.   Please explain briefly including which signal the removed one can be replaced with.

Site Maintained by: Greg Gibeling (gdgib <at> berkeley.edu)