CS 61C (Fall 2007)

Quiz 23

Two questions, submit as "quiz23". Due 2:45pm before lecture 10/22/2007.

1.

Give a single line Verilog statement that initializes a bit vector of 6 bits to the binary value 011100. The bit vector has been declared elsewhere as reg [5:0] op;.
Remember you cannot initialize and declare op within the same line (e.g. reg [5:0] op = ...; is not valid) because op has already been declared elsewhere!

2.

Section 4 of the "Verilog Tutorial" discusses code (on page 7) to test a 2-input multiplexor. Below is a slightly modified version, which will only print an error message when the actual output differs from the expected output.

module testmux2;
	reg	[2:0]		c;
	wire			f;
	reg			expected;

	mux2 myMux(.select(c[2]), .in0(c[0]), .in1(c[1]), .out(f));

	initial begin
		#0 c = 3’b000; expected=1’b0;
		repeat(7) begin
			#5
			if (expected ^ f) $display("[select in1 in0]=%b out=%b expected=%b", c, f, expected);
			#5
			c = c + 3’b001;
			if (c[2]) expected=c[1]; else expected=c[0];
		end
		#10 $stop;
	end
endmodule // testmux2

Normally, simulating this module would produce no output, as the mux2 module has been properly implemented, as has the testbench.

If we change the multiplexor instantiation (not to be confused with a function call) to mux2 myMux (.select(c[0]), .in0(c[1]), .in1(c[2]), .out(f)); and the if statement in the test code to

if (c[0]) expected=c[2]; 
    else expected=c[1];

, what will happen?

List, using Verilog constant notation, which values of c, if any, which will cause a line to be printed given the above modifications. In other words, after those changes, which inputs will cause the testbench to detect an error.