CS61C: Machine Structures. Fall 2007, UC Berkeley
Patterson and Hennessey Kernighan and Ritchie
CS61C Fall 2007
MWF 3pm-4pm 2050 VLSB





CS 61C (Fall 2007)

Project 5

Submit as "proj5".  Due 2:45pm 12/5/2007.

Administrative details

Submit your solution online by 2:45pm on Wednesday, December 5. Do this by creating a directory named proj5 that contains a file named proj5.c. From within that directory, type "submit proj5".

Problem

The files are provided in the directory ~cs61c/files/proj/5 augment a solution to proj3 to add a simulation of the cache. Complete the program by filling in appropriate procedures in proj5.c.

Simulator usage

The code in sim.c is similar to its proj3 counterpart. It is used as follows:

sim [-i -r -m -c -d -aarg -sarg -barg] inputfile
optioneffect
-i
-r
-m
-d
as in proj3
-c prints the contents of the cache after each instruction.
-aarg sets the cache associativity to arg. The default is 1 (i.e., direct-mapped); arg must be a power of 2.
-sarg sets the number of cache sets to arg. The default is 4 (i.e. four cache sets); arg must be a power of 2. Each set will have as many entries as the associativity of the cache.
-barg sets the cache block size to arg words. If this option is unspecified, the block size is set to 2; arg must be a power of 2.

Simulator Files

The following is a list of the framework files and their purposes. Download, or copy them from ~cs61c/files/proj/5/.

You are to complete the simulator by writing the unfinished code in the file proj5.c. Do not change the framework code or add any more source files; just fill in the frameworks where indicated. You may provide additional helper functions. The procedures that you must complete in proj5.c are:

AutoGrading Corner Cases

While these may seem like trivial corner cases, to some extent these details do reflect the real operation of a cache.  Of course, some of this is merely an outgrowth of our need to rely on the autograder, for which we really do apologize.

Testing

You should have more than enough code to test a processor at this point, given proj3 and proj4. However, you will need to be sure to exercise your cache thoroughly. A test program such as cache.s from lab12 is a decent start, though it certainly isn't the whole story.

Errors

There are two possible errors which can arise in the code you need to write. These are both documented in the comments for the relevant code.



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