Goals

This week you will get some more experience working with Verilog, building progressively larger module as we work up to proj4.  In particular, you will be learning to write your own logic and testbenches for very simple circuits this week.  In order to make the assignment easier, we've tied it in with the accumulator example from lecture.

Reading

• ModelSim Tutorial, especially the introduction which lists the sections relevant to CS61C. This document is periodically updated, make sure your copy is recent by checking the date at the top of the first page.
• Verilog Tutorial (Section 4 in particular)
• Lecture 24
• Verilog Circuit Rules
• Verilog Green Card

Setup

Work with a partner on these exercises.  You may wish to try someone new this week.

Copy the contents of ~cs61c/files/lab/9 to a suitable location in your home directory. Included are a number of Verilog files, including FullAdder.v and Add4.v for which you will implement both the module and the associated testbench.

This lab will be quite long if you have not done the reading.  Pace yourself, and move quickly.  If you get stuck, as your TA for help or talk to the groups around you.

Exercise 1 (2 points) - Full Adder

For this exercise you will be filling in the implementation of FullAdder.v and FullAdderTestBench.v.

1. Implement the FullAdder.v module based on slide 8 of Lecture24. You may use either continuous assign statements, or primitive gates as shown on the Verilog Green Card.
2. Design a testbench which tests all possible inputs using FullAdderTestBench.v as a starting place. You may find that section 4 of the Verilog Tutorial will make your life easier.
3. Show your TA a complete simulation of your full adder which proves that it works.
4. If you have extra time: automate your testbench as in Quiz23 to print an error message when your adder fails. You may wish to deliberately break your FullAdder module to test this feature.

Exercise 2 (1 points) - Add4

For this exercise you will be filling in the implementation of Add4.v and Add4TestBench.v.

1. Implement the Add4.v module based on slide 9 of Lecture24. You must implement this module structurally (remember HW7?), by instantiating your FullAdder implemented above. You may add as many wire declarations as you need.
2. Design a testbench which tests all possible inputs using Add4TestBench.v as a starting place. You may find that section 4 of the Verilog Tutorial will make your life easier, and you may wish to start from the above code.
3. Show your TA a complete simulation of your four bit adder which proves that it works.
4. If you have extra time: automate your testbench as in Quiz23 to print an error message when your adder fails. You may wish to deliberately break your Add4 module to test this feature.

Exercise 3 (1 points) - Accumulator

Many of the recent lectures on Synchronous Digital Systems (Lecture21 for example, and Quiz21) have used an accumulator, a circuit which calculates the sum of it's inputs as they are presented one per clock cycle, as an example.

1. Implement the Accumulator4.v module by instantiating your Add4 implemented above, and a Register4. You may add as many wire declarations as you need.
2. Show your TA a complete simulation of your four bit accumulator, using Accumulator4TestBench.v which proves that it works.
3. Explain to your TA at least 4 consecutive changes in the output of the accumulator, including what inputs caused those changes.
4. If you have extra time: use the given Accumulator4.v module to implement a four bit, binary counter in a separate file: Counter.v. This circuit will count 0, 1, 2, ..., 15, 0 repeating every 16 clock cycles. This is one of the most important circuits in digital logic, and the basis of many state machines and controllers.
5. If you have extra time: make your counter count down instead of up. Or you can try and make implement some other interesting number pattern.