CS 61C (Fall 2007)

Lab Assignment 8


In this lab you will learn to work with the Verilog HDL simulator program ModelSim.  This program, ModelSim, takes a textual representation of a circuit written in the Verilog Hardware Description Language (Verilog for short) and simulates it's behavior under a set of test inputs, provided by a short program called a testbench.  While the testbench is a sort of "program" the remainder of the Verilog you will be working with represents a circuit, a piece of hardware, rather than a program.  Do not confuse the two.

By the end of this lab you should be able to write some basic Verilog constructs, you should have a handle on the correspondence between a schematic and the Verilog which represents it, and you should be able use the ModelSim simulator for at least the simplest of tasks.




Work with a partner on these exercises.  You may wish to try someone new this week.

Copy the contents of ~cs61c/files/lab/8 to a suitable location in your home directory. Included are a number of Verilog files, including Mux4_2.v which you will implement, and Mux4_2TestBench.v which you will use to test your multiplexor.

Exercise 1 (4 points) - 4-bit wide 2-Input Mux

In this part of the lab you will build a simple 4-bit wide 2-input multiplexor using nothing more than a 1-bit wide 2-input multiplexor.  This should acquaint you with the basic Verilog syntax for module instantiation, and will give you a chance to try your hand at simulating the resulting circuit.

  1. Draw a schematic diagram of a 4-bit wide 2-input multiplexor showing how you will implement it using 1-bit wide 2-input multiplexors.

  2. Read through Mux1_2.v and make sure understand it.  In particular this will show you how to declare a module with inputs & outputs, how comments in Verilog can be used, and one of the simplest and most powerful ways to specify digital logic using Verilog. Answer this question: why are the inputs named the way they are?

  3. Translate your schematic diagram from part (a) above into Verilog in Mux4_2.v. Shown below are two example module instantiations. The italic text represents fields which you must fill in.

       modulename instancename(.second_portname(second_wirename), .first_portname(first_wirename));
       modulename instancename(first_wirename, second_wirename);
  4. Simulate your multiplexor by loading Mux4_2TestBench.v, Mux4_2.v and Mux1_2.v into ModelSim. To learn how to do this, please refer to the ModelSim Tutorial. You should simulate your circuit for 50ns with the command restart -f; run 60ns. This will show you six example inputs.

  5. Show your TA the schematic, you explanation of the input names in Mux1_2.v and the wave window of ModelSim showing all of the wires inside your Mux4_2 module simulated for 50ns.  Explain the relationships between the input and output signals in the wave window.