CS 61C (Fall 2007)
Lab Assignment 8
In this lab you will learn to work with the Verilog HDL simulator program ModelSim. This program, ModelSim, takes a textual representation of a circuit written in the Verilog Hardware Description Language (Verilog for short) and simulates it's behavior under a set of test inputs, provided by a short program called a testbench. While the testbench is a sort of "program" the remainder of the Verilog you will be working with represents a circuit, a piece of hardware, rather than a program. Do not confuse the two.
By the end of this lab you should be able to write some basic Verilog constructs, you should have a handle on the correspondence between a schematic and the Verilog which represents it, and you should be able use the ModelSim simulator for at least the simplest of tasks.
ModelSim is the name of the graphical HDL simulator we will be using for this lab
ssh -X cory, for ModelSim you must use
ssh -X ilinux1,
ssh -X ilinux2or
ssh -X ilinux3, as ModelSim is not installed on Nova.
Verilog is the HDL you will be using for the next few weeks in this class.
always, etc...) in a circuit will result in a very low grade for that assignment. If you are unclear whether a certain language construct is suitable for use in a circuit, ask your TA or post to the newsgroup.
Work with a partner on these exercises. You may wish to try someone new this week.
Copy the contents of ~cs61c/files/lab/8 to a suitable location in
your home directory. Included are a number of Verilog files, including
Mux4_2.v which you will implement, and
Mux4_2TestBench.v which you will use
to test your multiplexor.
In this part of the lab you will build a simple 4-bit wide 2-input multiplexor using nothing more than a 1-bit wide 2-input multiplexor. This should acquaint you with the basic Verilog syntax for module instantiation, and will give you a chance to try your hand at simulating the resulting circuit.
Draw a schematic diagram of a 4-bit wide 2-input multiplexor showing how you will implement it using 1-bit wide 2-input multiplexors.
Mux1_2.v and make sure understand it. In particular this
will show you how to declare a module with inputs & outputs, how comments in
Verilog can be used, and one of the simplest and most powerful ways to specify digital
logic using Verilog. Answer this question: why are the inputs named the way they are?
Translate your schematic diagram from part (a) above into Verilog in
Shown below are two example module instantiations. The italic text represents fields which you must fill in.
modulename instancename(.second_portname(second_wirename), .first_portname(first_wirename)); modulename instancename(first_wirename, second_wirename);
Mux1_2in this case. Note that this is the name used in the module declaration, which by convention is the same as the filename
mux1_2) within a higher level module (
mux4_2), each one needs a name so that you can examine them (add their signals to the Wave window) individually during simulation.
.portname(wirename)to connect the local wire with name wirename to the port named portname. If the connections are specified this way, they may appear in any order. This is the prefered method of connecting wires to ports.
Simulate your multiplexor by loading
Mux1_2.v into ModelSim.
To learn how to do this, please refer to the ModelSim Tutorial. You should simulate
your circuit for
50ns with the command
restart -f; run 60ns. This will show you six example inputs.
Show your TA the schematic, you explanation of the input names in
Mux1_2.v and the wave window of ModelSim
showing all of the wires inside your
Mux4_2 module simulated for 50ns.
Explain the relationships between the input and output signals in the wave window.