Goals

In this lab you will learn to work with the Verilog HDL simulator program ModelSim.  This program, ModelSim, takes a textual representation of a circuit written in the Verilog Hardware Description Language (Verilog for short) and simulates it's behavior under a set of test inputs, provided by a short program called a testbench.  While the testbench is a sort of "program" the remainder of the Verilog you will be working with represents a circuit, a piece of hardware, rather than a program.  Do not confuse the two.

By the end of this lab you should be able to write some basic Verilog constructs, you should have a handle on the correspondence between a schematic and the Verilog which represents it, and you should be able use the ModelSim simulator for at least the simplest of tasks.

Reading

• ModelSim Tutorial, especially the introduction which lists the sections relevant to CS61C. This document is periodically updated, make sure your copy is recent by checking the date at the top of the first page.
• Verilog Tutorial (Part 1 & 2 minimum, more recommended)
• P&H: B.4, B.8 (recommended)

Background

• ModelSim is the name of the graphical HDL simulator we will be using for this lab

  • You absolutely must read the ModelSim Tutorial in order to complete this lab.
  • Whereas for MARS you must us ssh -X cory, for ModelSim you must use ssh -X ilinux1, ssh -X ilinux2 or ssh -X ilinux3, as ModelSim is not installed on Nova.
  • Those of you interested in running ModelSim at home can get a copy here.
  • General ModelSim usage questions should get posted to the newsgroup ASAP.

• Verilog is the HDL you will be using for the next few weeks in this class.

  • The Verilog Tutorial is a good starting place.
  • In general we will give you plenty of Verilog to allow you to learn it by example.
  • Keep in mind that Verilog contains capabilities for describing testbenches (programs for simulation) and actual circuits. The Verilog you write must match up with it's inteded use. Using testbench constructs (initial, always, etc...) in a circuit will result in a very low grade for that assignment. If you are unclear whether a certain language construct is suitable for use in a circuit, ask your TA or post to the newsgroup.

Setup

Work with a partner on these exercises.  You may wish to try someone new this week.

Copy the contents of ~cs61c/files/lab/8 to a suitable location in your home directory. Included are a number of Verilog files, including Mux4_2.v which you will implement, and Mux4_2TestBench.v which you will use to test your multiplexor.

Exercise 1 (4 points) - 4-bit wide 2-Input Mux

In this part of the lab you will build a simple 4-bit wide 2-input multiplexor using nothing more than a 1-bit wide 2-input multiplexor.  This should acquaint you with the basic Verilog syntax for module instantiation, and will give you a chance to try your hand at simulating the resulting circuit.

1. Draw a schematic diagram of a 4-bit wide 2-input multiplexor showing how you will implement it using 1-bit wide 2-input multiplexors.

   • Your circuit, and your schematic, should be composed entirely of 1-bit wide 2-input multiplexors such as you have seen in the reading and quiz20.
   • Go back and label all of the inputs, outputs and wires with meaningful names.
   • Finally, draw a large box around your schematic which has the same inputs and outputs as shown in Mux4_2.v

2. Read through Mux1_2.v and make sure understand it.  In particular this will show you how to declare a module with inputs & outputs, how comments in Verilog can be used, and one of the simplest and most powerful ways to specify digital logic using Verilog. Answer this question: why are the inputs named the way they are?

3. Translate your schematic diagram from part (a) above into Verilog in Mux4_2.v. Shown below are two example module instantiations. The italic text represents fields which you must fill in.

      modulename instancename(.second_portname(second_wirename), .first_portname(first_wirename));
      modulename instancename(first_wirename, second_wirename);

   • The modulename is the name of the module you wish to instantiate: Mux1_2 in this case. Note that this is the name used in the module declaration, which by convention is the same as the filename
   • The instancename is a name for this instance of the specified module. Since there may be multiple instances of a lower level module (mux1_2) within a higher level module (mux4_2), each one needs a name so that you can examine them (add their signals to the Wave window) individually during simulation.
   • The first declaration uses named connections for the ports, where we write .portname(wirename) to connect the local wire with name wirename to the port named portname. If the connections are specified this way, they may appear in any order. This is the prefered method of connecting wires to ports.
   • The second declaration uses the less popular ordered connections, where we list the local wires in the order of the ports to which they connect, somewhat similar to the way arguments and values are lined up during a C function call. However, always remember a module instantiation creates a permanent physical copy of a circuit, and is nothing like a function call.

4. Simulate your multiplexor by loading Mux4_2TestBench.v, Mux4_2.v and Mux1_2.v into ModelSim. To learn how to do this, please refer to the ModelSim Tutorial. You should simulate your circuit for 50ns with the command restart -f; run 60ns. This will show you six example inputs.

5. Show your TA the schematic, you explanation of the input names in Mux1_2.v and the wave window of ModelSim showing all of the wires inside your Mux4_2 module simulated for 50ns.  Explain the relationships between the input and output signals in the wave window.