CS 61C (Fall 2007)

Lab Assignment 10



Goals

The goal of this week is to get you started on proj4.  In particular, you will be implementing the fetch logic, and your first instruction: break. Our goal is to ensure that your are able work with a complete processor design, rather than simply copying Figure 5.24 or 5.17.

Reading

Setup

Work with a partner on these exercises.  You may wish to try someone new this week.

While proj4 is a one person assignment, you will do this lab with a partner.  At the end you should both have written your own Verilog, and we will ask you each to explain different parts of it.  However you should feel free, during the lab, to look at each others Verilog and assembly, and explain it in detail.

Exercise 1 (1 point) - Test Program

Write a short test program. For the purposes of this lab, you will be implementing the break instruction only. All other instructions may be interpreted as nop, meaning they have no effect.

Your test program must contain at least four different non-break instructions (which may be treated as nops during this lab) followed by a break instruction with a non-zero BreakCode. If you have already implemented more instructions outside of lab, feel free to show them off.  We ask you to use four different instructions so that you have some confidence that your break detection logic will work correctly.

Show your TA your test program, and the contents of the resulting .text segment dump (remember to use HexListing format). You can find instructions for generating these files in proj4.

Exercise 2 (3 points) - Fetch Logic

Within your CPU.v module, you will need a PC register, some logic to update it, an instruction memory and some logic to recognize and handle the break instruction.

For this exercise you will need to implement the fetch logic of your CPU.  In particular when you are done your processor must be able to load the program you wrote in Exercise1, and run it properly (treating any non-break instructions as nops).  Probably the most complicated part of this lab will be working with the ROM module from Blocks.v, be sure to refer to P&H Figure 5.17 & 5.24 and the proj4 assignment if you get stuck.  As mentioned in the proj4 spec, your PC should start at 0.

After you have implemented the fetch logic (PC, PC+4, Instruction Memory, etc...) you will move on to implementing the control logic nessecary to properly decode the break instruction in Control.v.  As you do this please read the instructions about allowed Verilog constructs (see the introduction of proj4) carefully.  In particular, you will find that the simple == operator is entirely disallowed, and you will need to implement the same functionality using primitive gates.  Notice that Control.v should not be responsible for generating the BreakCode, as that is the job of the datapath.  As you work, you will probably find the you need to modify the list of ports on the Control.v module in order to properly generate the Break output, as mentioned in proj4, this is allowed.

Once you are done implementing your fetch & decode logic, you will want to simulate your partial processor implementation running your MIPS program from Exercise1.  To do this, you will need to rename the dump files to dump.text and dump.data, and put them in the same directory as your ModelSim project.  Note that this is the directory where the vsim.wlf and transcript files are, which is not necessarily where your Verilog files are.

Show your TA the Verilog and schematic diagram for your processor, the diagnostic messages printed by our testbench (or your own if you have one) and the wave window. Be prepared to explain the operation of all the signals in your CPU file over the few clock cycles before the break instruction.