## Homework Assignment 8

Two exercises, submit as "hw8".  Due 2:45pm before lecture 10/31/2007.

### Goals

This assignment is intended to give you more practice with the Register state element, and with finite state machines in general.

### Exercise 1 (4 points)

The Verilog module whose framework appears below is intended to output 1 if its 2-bit input signal is the same at this clock signal as it was at the last, and 0 otherwise. Using only structural Verilog (module instantiations) and primitive gate instantiations, complete the module. This means you may not use `assign`, `always` or `initial`.  You should fill your implementation into ``` StillTheSame.v```.

Also provide a test bench module that tests four cases:

• both bits match
• the first bit matches
• the second bit matches
• neither bit matches
```module StillTheSame(Clock, Reset, In, Out);
input		Clock, Reset;
input	[1:0]	In;
output		Out;

// EXTRA WIRES GO HERE.

// Instantiate the register, you should fill in the blanks
Register2 State(.Clock(Clock), .In(________) , .Out(________) , .Reset(Reset));

// YOUR LOGIC GOES HERE.  USE ONLY STRUCTURAL VERILOG.
// Generate the output:
____________ ( Out , ____________ , ____________ );
endmodule
```

### Exercise 2 (4 points)

Consider a circuit that moves a 1 bit back and forth among a pair of 0 bits. Resetting the circuit puts the 1 at the left of the two 0's; each tick of the clock then moves the 1 as shown below.   This is a fairly common special effect from old science fiction movies for example.

```	100
010
001
010
100
010
001
010
100
...
```

#### Part a

For this part of the problem you will be designing the FSM (Finite State Machine).  For background, you may wish to refer to Lecture22.

List the states for this circuit and draw a state diagram that shows how the 1 bit moves from one state to the next. Assume that transitions between states correspond only to clock pulses. Don't worry about what state the device starts in.

You can submit the diagram as ASCII line art, JPEG, GIF, PDF or SVG.  If your favorite graphics format isn't listed, ask on the newsgroup and we'll think about it.

#### Part b

Design a Verilog simulation of this circuit. It's controlled only by the clock and the reset signal; there are no other inputs. Use only structural Verilog and registers, and separate the "next state" logic into its own module.

• The main module in `FSM.v` with inputs `Clock` and `Reset` and a three bit output `Out`.
• The next state module in `NextState.v`
• A register module in `Register2.v`, feel free to modify one of the registers we've given you on a past assignment.
• A testbench in `FSMTestBench.v`