CS 61C (Fall 2007)
Homework Assignment 7One exercise, submit as "hw7". Due 2:45pm before lecture 10/26/2007.
This homework is intended as extra practice working with the Verilog HDL and ModelSim, to be done after you have completed Lab8. This assignment will also prepare you for proj4, which require you to work with ModelSim extensively. As such, if you intend to download the student edition of ModelSim to run on your computer at home, now is the time.
ModelSim is the name of the graphical HDL simulator we will be using for this homework
ssh -X cory, for ModelSim you must use
ssh -X ilinux1,
ssh -X ilinux2or
ssh -X ilinux3, as ModelSim is not installed on Nova.
Verilog is the HDL you will be using for the next few weeks in this class.
always, etc...) in a circuit will result in a very low grade for that assignment. If you are unclear whether a certain language construct is suitable for use in a circuit, ask your TA or post to the newsgroup.
Copy the contents of ~cs61c/files/hw/7 to a suitable location in
your home directory. Included are a number of Verilog files, including
ParallelSort.v which you will implement, and
ParallelSortTestBench.v which you will use
to test your and sorter implementation.
Submit your solution by creating a directory named hw7 that contains your copy
ParallelSort.v. From within
that directory, type submit hw7. Note that we will be autograding
this assignment on a participation basis. As long as your code is vaguely correct
you will receive credit. This assignment is intended as easy practice.
This is not a partnership assignment. Hand in your own work.
Building on your newfound ability to simulate circuits from lab8, and translate from schematics to Verilog, this homework will have you implement a 4-bit 4-input circuit which will sort it's inputs in a single clock cycle (hence the parallel or combinational sort).
Shown below is a schematic of the
Your job is to translate this schematic into Verilog in
that we have already done some of the work for you, and that you should feel free to create new wires as needed, but you may not
add inputs or outputs. Before you begin, you may wish to take inventory of the Verilog modules you have, and examine them in detail.
In order to test your implementation you should simulate it for at least 60ns, which will show five example inputs.
If you have a few extra minutes:
Exchange4instanes. Is it possible? Why or why not?
Exchange4instances by sharing them over time?