CS 61C (Fall 2007)

Homework Assignment 7

One exercise, submit as "hw7".  Due 2:45pm before lecture 10/26/2007.


This homework is intended as extra practice working with the Verilog HDL and ModelSim, to be done after you have completed Lab8. This assignment will also prepare you for proj4, which require you to work with ModelSim extensively. As such, if you intend to download the student edition of ModelSim to run on your computer at home, now is the time.




Copy the contents of ~cs61c/files/hw/7 to a suitable location in your home directory.  Included are a number of Verilog files, including ParallelSort.v which you will implement, and ParallelSortTestBench.v which you will use to test your and sorter implementation.

Submission instructions

Submit your solution by creating a directory named hw7 that contains your copy of ParallelSort.v. From within that directory, type submit hw7.  Note that we will be autograding this assignment on a participation basis. As long as your code is vaguely correct you will receive credit. This assignment is intended as easy practice.

This is not a partnership assignment. Hand in your own work.

Parallel/Combinational Sorter

Building on your newfound ability to simulate circuits from lab8, and translate from schematics to Verilog, this homework will have you implement a 4-bit 4-input circuit which will sort it's inputs in a single clock cycle (hence the parallel or combinational sort).

Shown below is a schematic of the ParallelSort module. Your job is to translate this schematic into Verilog in ParallelSort.v. Notice that we have already done some of the work for you, and that you should feel free to create new wires as needed, but you may not add inputs or outputs. Before you begin, you may wish to take inventory of the Verilog modules you have, and examine them in detail.

In order to test your implementation you should simulate it for at least 60ns, which will show five example inputs.

If you have a few extra minutes:

ParallelSort - A combinational Sorter

If the above diagram is not visible for you, please download the Adobe SVG viewer