CS 61C (Fall 2007) |
Homework Assignment 10Two exercises. Due 2:45pm before lecture 11/14/2007. |
This assignment is intended to give you more practice with aspects of the MIPS pipeline.
Submit a file named "hw10.txt" as hw10.
Consider the following function, which when given as arguments a pointer to the start of an integer array values and an integer n, returns the sum of the first n elements of values.
# $a0 contains array address, $a1 contains # elements firstNsum: move $t0,$a0 # current element address move $t1,$0 # current element index move $v0,$0 # sum loop: beq $t1,$a1,gotsum lw $t2,0($t0) # get element add $v0,$v0,$t2 addi $t0,$t0,4 addi $t1,$t1,1 j loop gotsum: jr $ra
The following two instructions are being proposed for addition to the MIPS hardware instruction set.
push $rt,($rs)
stores the value from $rt into the memory address contained in $rs,
then subtracts 4 from $rs. Note that no offset is specified.
lwz $rt,offset($rs) (Load Word if Zero)
loads the value from the selected memory address
into $rt if the old value in $rt is 0,
otherwise does nothing.
For each of the two instructions, provide the following information.
Indicate whether the instruction can be implemented in a way that is consistent with the existing five-stage pipeline, but that doesn't add any extra functional units such as another ALU or memory port. (Extra control signals, wires, and multiplexors are OK.)
If your answer to part a is "yes, it can", list what happens in stages 3, 4, and 5 when processing the instruction. If your answer to part a is "no, it can't", explain why.