CS61C Project 3: Verilog MIPS Processor
Due Wednesday, November 24th, 11:59pm
November 21, 2004
This project will test your understanding of Verilog and the implementation of a single cycle CPU. You will be implementing a simple processor that is capable of simulating a subset of real MIPS instructions. This is an individual project not to be done in partnership. All work handed in must be your own and not result from collaboration with others. Reading: Sections 5.1 through 5.3 and Appendix C.2 in P&H.
Andrew Lawrence Schultz