####
# Makefile - Makefile to compile the processor, run the tests, and do
#            the submission.  The following make's are available:
#
#  make - Compile the processor
#
#  make tests - Compile the processor and run all of the specified tests
#               If you run "make tests > foo" it will save the output of
#               the tests to "foo"
#
#  make submittests - Compile the processor with the master copies and
#                     run tests before submission
#
#  make submit - Actually submit the project
#
#  make clean - Delete the vvp file
####

VERILOG=iverilog-0.6
SUBMIT=submit
PROJ=proj3

OUTPUT=cpu.vvp
CPU=cpu.v
BLOCKS=blocks.v
TESTBENCH=testbench.v
MPATH=/home/ff/cs61c/hw/proj3

# Add names of new tests here to have them run
TESTS=inc-loop simple.beq simple.lw.sw simple.rfmt

all: compile

compile:
	$(VERILOG) -tvvp -o $(OUTPUT) -Wall $(BLOCKS) $(TESTBENCH) $(CPU) 

submitcompile:
	$(VERILOG) -tvvp -o $(OUTPUT) -Wall $(MPATH)/$(BLOCKS) \
		$(MPATH)/$(TESTBENCH) $(CPU) 

tests: compile
	cd tests;                          \
	for i in ${TESTS}; do              \
		echo "";                   \
                echo "***";                \
		echo "* Running test $$i"; \
		echo "***";                \
		echo "";                   \
		./trycpu ../cpu.vvp $$i;   \
	done	

submittests: clean submitcompile tests

submit: 
	$(SUBMIT) $(PROJ)

clean:
	rm -rf cpu.vvp