Altera Parts History

Compiled by John Lazzaro


1984: EP 300

The first product. An erasable programmable logic device (EPLD) was manufactured using a 3-micron CMOS EPROM technology and required ultraviolet light to erase the device prior to reprogramming. The EP300 device had 300 gates and 8 macrocells. Followed by larger parts such as EP 1200, with 1,200 gates and 28 macrocells.

Data sheet.

1988: MAX 5000

High-density complex programmable logic device (CPLD). Patented redundancy technology delivers reduction of defects and increased yields (first introduced in 650-nm, this key technology continues to deliver increased yields in Altera 65-nm devices today).

Data sheet from http://www.altera.com/literature/ds/m5000.pdf, and locally here.

1992: Flex 8000

Altera's first field programmable gate array (FPGA).

Data Sheet from http://www.altera.com/literature/ds/dsf8k.pdf, and locally here.

1994: MAX 9000

JTAG in-system reprogrammable CPLD.

Data sheet: http://www.altera.com/literature/ds/m9000.pdf, and locally here.

1995: FLEX 10K

FPGA with embedded block RAM.

Data sheet: http://www.altera.com/literature/ds/dsf10k.pdf, and locally here.

1998: FLEX 6000

First FLEX appearance in FPGA conference (apparently).

Data sheet: http://www.altera.com/literature/ds/dsf6k.pdf, and locally here.

Conference publication: http://doi.acm.org/10.1145/275107.275115, and locally here.

Xcell-style webpage story: http://www.altera.com/products/devices/flex6k/f6k-index.html.

1999: APEX EP20K1500E

More than 1.5 million gates.

Data sheet: http://www.altera.com/literature/ds/apex.pdf, and locally here.

Conference publication: http://doi.acm.org/10.1145/329166.329173, and locally here.

2000: ARM-based Excalibur devices

FPGA with hard embedded processor. Data sheet: http://www.altera.com/literature/ds/ds_arm.pdf, and locally here.

Xcell-style webpage story: http://www.altera.com/products/devices/arm/arm-index.html.

2001: Mercury FPGA

180nm FPGA with embedded transceivers. Data sheet: http://www.altera.com/literature/ds/dsmercury.pdf, and locally here.

Conference publication: http://doi.acm.org/10.1145/503048.503050, and locally here.

2002: Stratix FPGA

FPGA with embedded DSP blocks.

Data sheet: http://www.altera.com/literature/lit-stx.jsp.

Conference publication: http://doi.acm.org/10.1145/611817.611821, and locally here.

2002: Cyclone FPGAs

Low-cost FPGAs.

Data Sheet: http://www.altera.com/literature/lit-cyc.jsp.

Conference publication (CICS): http://altera.us/literature/cp/cyclone-lc-hp-fpga-423.pdf, and locally here.

2003: Stratix GX

FPGA with LVDS transceivers.

Data Sheet: http://www.altera.com/literature/lit-sgx.jsp.

2004: Stratix II

FPGA with larger LUTs.

Data Sheet: http://www.altera.com/literature/lit-stx2.jsp.

Conference publication: http://doi.acm.org/10.1145/1046192.1046195, and locally here.

2005: Hardcopy II

Earlier versions go back to 2001; Hardcopy II is the earliest version that is well-documentated online.

Data Sheet: http://www.altera.com/products/devices/hardcopy-asics/hardcopy-ii/hr2-index.jsp.

Conference publication: http://portal.acm.org/citation.cfm?id=1131355.1131369&coll=GUIDE&dl=GUIDE&CFID=100056097&CFTOKEN=41588013, and locally here.

2005: Cyclone II

90-nm low-cost FPGA.

Data Sheet: http://www.altera.com/literature/lit-cyc2.jsp.

2006: Stratix II GX

FPGA with transcievers up to 6 Gbps.

Data Sheet: http://www.altera.com/literature/lit-s2gx.jsp.

2006: Stratix III

65nm refresh of Stratix II

Data Sheet: http://www.altera.com/literature/lit-stx3.jsp.

Conference paper (covers Stratix III and IV): http://doi.acm.org/10.1145/1508128.1508135, and locally here.

2007: Cyclone III

65nm refresh of Cyclone II

Data Sheet: http://www.altera.com/literature/lit-cyc3.jsp.

2007: Arria GX

Low-cost transceiver-centric FPGA

Data Sheet: http://www.altera.com/literature/lit-agx.jsp.

2008: Stratix IV

40-nm refresh of Stratix III

Data Sheet: http://www.altera.com/literature/lit-stratix-iv.jsp.

Conference paper (covers Stratix III and IV): http://doi.acm.org/10.1145/1508128.1508135, and locally here.

2009: Stratix IV GT

FPGA with 11.3 Gbps transceiver support.

Data Sheet: http://www.altera.com/literature/lit-stratix-iv.jsp.

2009: Arria II GX

40-nm refresh of Arria GX (low-cost transciever FPGA)

Data Sheet: http://www.altera.com/literature/lit-arria-ii-gx.jsp.

2009: Cyclone III LS

Low-cost FPGA with bitstream protection support.

Data Sheet: http://www.altera.com/literature/lit-cyc3.jsp.

2010: Stratix V

28-nm Stratix IV refresh announcement.

Data sheet: http://www.altera.com/literature/lit-stratix-v.jsp.

2010: Cyclone IV

Incremental update of Cyclone series.

Data sheet: http://www.altera.com/literature/lit-cyclone-iv.jsp.